SENSE AMPLIFIER HAVING LOOP GAIN CONTROL
    3.
    发明申请
    SENSE AMPLIFIER HAVING LOOP GAIN CONTROL 有权
    具有环路增益控制的感应放大器

    公开(公告)号:US20140167848A1

    公开(公告)日:2014-06-19

    申请号:US14188295

    申请日:2014-02-24

    Inventor: Seong-Hoon Lee

    Abstract: Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain, and further including an amplifier stage coupled to the bias circuit to receive the bias voltage and configured to amplify a input current at an input-output node, a loop gain of the current amplifier stage is controlled at least in part to the bias voltage.

    Abstract translation: 公开了用于放大电流输入的存储器,感测放大器和放大电流输入的方法,包括读出放大器,其包括偏置电路,该偏置电路被配置为提供具有响应于保持基本上恒定的环路增益的幅度的偏置电压,并且还包括耦合到 偏置电路以接收所述偏置电压并且被配置为放大输入 - 输出节点处的输入电流,所述电流放大器级的环路增益至少部分地被控制为所述偏置电压。

    Sense amplifier having loop gain control
    4.
    发明授权
    Sense amplifier having loop gain control 有权
    具有环路增益控制的感应放大器

    公开(公告)号:US09013942B2

    公开(公告)日:2015-04-21

    申请号:US14188295

    申请日:2014-02-24

    Inventor: Seong-Hoon Lee

    Abstract: Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain, and further including an amplifier stage coupled to the bias circuit to receive the bias voltage and configured to amplify a input current at an input-output node, a loop gain of the current amplifier stage is controlled at least in part to the bias voltage.

    Abstract translation: 公开了用于放大电流输入的存储器,感测放大器和放大电流输入的方法,包括读出放大器,其包括偏置电路,该偏置电路被配置为提供具有响应于保持基本上恒定的环路增益的幅度的偏置电压,并且还包括耦合到 偏置电路以接收所述偏置电压并且被配置为放大输入 - 输出节点处的输入电流,所述电流放大器级的环路增益至少部分地被控制为所述偏置电压。

    Current sense amplifiers, memory devices and methods

    公开(公告)号:US10236052B2

    公开(公告)日:2019-03-19

    申请号:US15592436

    申请日:2017-05-11

    Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

    Current mode sense amplifier with load circuit for performance stability
    6.
    发明授权
    Current mode sense amplifier with load circuit for performance stability 有权
    具有负载电路的电流模式读出放大器,性能稳定

    公开(公告)号:US09484074B2

    公开(公告)日:2016-11-01

    申请号:US14258317

    申请日:2014-04-22

    CPC classification number: G11C7/065 G11C7/062 G11C2207/063

    Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.

    Abstract translation: 公开了一种存储器,电流模式读出放大器及其操作方法,包括一个包括交叉耦合的p沟道晶体管和耦合到交叉耦合的p沟道晶体管的负载电路的电流模式读出放大器。 负载电路被配置为提供至少部分地控制电流模式读出放大器的环路增益的电阻,负载电路至少包括被动电阻。

    SIGNAL DRIVER CIRCUIT HAVING ADJUSTABLE OUTPUT VOLTAGE FOR A HIGH LOGIC LEVEL OUTPUT SIGNAL
    9.
    发明申请
    SIGNAL DRIVER CIRCUIT HAVING ADJUSTABLE OUTPUT VOLTAGE FOR A HIGH LOGIC LEVEL OUTPUT SIGNAL 有权
    具有高逻辑电平输出信号的可调输出电压的信号驱动电路

    公开(公告)号:US20140062531A1

    公开(公告)日:2014-03-06

    申请号:US14077117

    申请日:2013-11-11

    Inventor: Seong-Hoon Lee

    Abstract: A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage.

    Abstract translation: 具有用于高逻辑电平输出信号的可调输出电压的信号驱动器电路。 信号驱动器电路包括:信号驱动器,被配置为输出具有第一电压的第一逻辑电平信号,并输出具有根据输入信号的第二电压的第二逻辑电平信号。 耦合到信号驱动器的电压控制电压电源为第一逻辑电平信号提供第一电压。 由压控电压提供的第一电压的大小基于偏置电压。 偏置电压发生器可以耦合到压控电压源以提供偏置电压。

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