公开(公告)号：US20250104792A1

公开(公告)日：2025-03-27

申请号：US18751936

申请日：2024-06-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YASUSHI MATSUBARA ,  YOSHINORI FUJIWARA ,  TAKUYA TAMANO

IPC: G11C29/18 ,  G11C29/12

Abstract: According to one or more embodiments of the disclosure, an apparatus comprises a memory device and a bias temperature instability (BTI) controller. The BTI controller generates and outputs a command and address signal for memory testing. The command and address signal causes the memory device in the idle state to operate for the testing.

公开(公告)号：US20240331794A1

公开(公告)日：2024-10-03

申请号：US18612284

申请日：2024-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TAKAMASA SUZUKI ,  YASUSHI MATSUBARA ,  HARUTAKA MAKABE

IPC: G11C29/44 ,  G11C29/18 ,  G11C29/24

CPC classification number: G11C29/44 ,  G11C29/18 ,  G11C29/24 ,  G11C2029/1806

Abstract: Self-test circuits of memory devices disclosed herein may include circuitry that adjusts the correspondence between logical and physical addresses to match pre-repair mapping of memory locations. That is, if a memory device has been repaired by remapping logical addresses to new physical addresses, the circuitry of the test circuit restores the pre-repair mapping of the memory device in some examples. In some examples, an unused global column redundancy data path may be repurposed to provide repair information to the self-test circuit to implement the pre-repair mapping.

公开(公告)号：US20240265992A1

公开(公告)日：2024-08-08

申请号：US18402096

申请日：2024-01-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YASUSHI MATSUBARA ,  MINORU SOMEYA

IPC: G11C29/00 ,  G11C17/18 ,  G11C29/44

CPC classification number: G11C29/787 ,  G11C17/18 ,  G11C29/44 ,  G11C29/76

Abstract: An apparatus includes a memory chip including a plurality of fuse units, and a controller chip. Each fuse unit includes a fuse array having a plurality of fuse cells, a first register, and a second register. The controller is configured to set the fuse address in the second register included in selected one or more of the plurality of fuse units, set the match signal in the first register included in the selected one or more of the plurality of fuse units, and send a blow signal to the memory chip. Each of the selected one or more of the plurality of fuse units is configured to blow one of the plurality of fuse cells selected by the fuse address stored in the second register responsive to the blow signal.