公开(公告)号：US20170052899A1

公开(公告)日：2017-02-23

申请号：US14828587

申请日：2015-08-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ye-Jyun Lin ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Chia-Lin Yang

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0897 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0685 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/1044 ,  G06F2212/225

Abstract: A buffer cache device used to get at least one data from at least one application is provided, wherein the buffer cache device includes a first-level cache memory, a second-level cache memory and a controller. The first-level cache memory is used to receive and store the data. The second-level cache memory has a memory cell architecture different from that of the first-level cache memory. The controller is used to write the data stored in the first-level cache memory into the second-level cache memory.

Abstract translation: 提供了用于从至少一个应用获得至少一个数据的缓冲器高速缓存设备，其中缓冲器高速缓存设备包括第一级高速缓冲存储器，二级高速缓存存储器和控制器。 第一级高速缓存用于接收和存储数据。 第二级高速缓冲存储器具有与第一级高速缓冲存储器不同的存储单元架构。 控制器用于将存储在第一级高速缓冲存储器中的数据写入二级高速缓冲存储器。

公开(公告)号：US09672067B2

公开(公告)日：2017-06-06

申请号：US14696657

申请日：2015-04-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ye-Jyun Lin ,  Hsiang-Pang Li ,  Shang-Xuan Zou ,  Chia-Lin Yang

IPC: G06F9/48

CPC classification number: G06F9/4881 ,  G06F9/4812

Abstract: A data processing system comprises a storage device, an interface module and a scheduler. The interface module is configured to dispatch a non-prioritized request via a first data path, and to transfer application-level information of an application via a second data path. The scheduler, coupled to the first and second data path, is configured to enable an access to the storage device according to the non-prioritized request and the application-level information respectively received from the first and second data paths.

公开(公告)号：US09171616B2

公开(公告)日：2015-10-27

申请号：US14165136

申请日：2014-01-27

Applicant: Macronix International Co., Ltd.

Inventor： Ren-Shuo Liu ,  De-Yu Shen ,  Chia-Lin Yang ,  Ye-Jyun Lin ,  Cheng-Yuan Wang

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0069

Abstract: A method for operating a memory includes receiving a command to program a data value at a memory cell, and an indication of which write mode in a plurality of write modes to use. Write modes in the plurality are characterized by different sets of resistance ranges that correspond to data values stored in the memory cell. The method includes executing a program operation according to the indicated one in the plurality of write modes to program the data value in the memory cell. The plurality of write modes includes a first write mode and a second write mode corresponding to shorter data retention than the first write mode. The first and second write modes are characterized by first and second sets of resistance ranges in the different sets of resistance ranges. The method includes periodically refreshing data values in memory cells storing data in the second write mode.

Abstract translation: 一种用于操作存储器的方法包括接收对存储器单元的数据值进行编程的命令以及使用多种写入模式中的哪个写入模式的指示。 多个中的写入模式的特征在于对应于存储在存储单元中的数据值的不同的电阻范围。 该方法包括根据多个写入模式中指示的一个执行程序操作，以对存储单元中的数据值进行编程。 多个写入模式包括对应于比第一写入模式更短的数据保持的第一写入模式和第二写入模式。 第一和第二写入模式的特征在于不同的电阻范围集中的第一组和第二组电阻范围。 该方法包括在存储第二写入模式的数据的存储单元中周期性地刷新数据值。

公开(公告)号：US20160154674A1

公开(公告)日：2016-06-02

申请号：US14696657

申请日：2015-04-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ye-Jyun Lin ,  Hsiang-Pang Li ,  Shang-Xuan Zou ,  Chia-Lin Yang

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/4812

Abstract: A data processing system comprises a storage device, an interface module and a scheduler. The interface module is configured to dispatch a non-prioritized request via a first data path, and to transfer application-level information of an application via a second data path. The scheduler, coupled to the first and second data path, is configured to enable an access to the storage device according to the non-prioritized request and the application-level information respectively received from the first and second data paths.

Abstract translation: 数据处理系统包括存储设备，接口模块和调度器。 接口模块被配置为经由第一数据路径分派非优先化请求，并且经由第二数据路径传送应用的应用级信息。 耦合到第一和第二数据路径的调度器被配置为使得能够根据从第一和第二数据路径分别接收的非优先级请求和应用级信息来访问存储设备。

公开(公告)号：US20150043274A1

公开(公告)日：2015-02-12

申请号：US14165136

申请日：2014-01-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ren-Shuo Liu ,  De-Yu Shen ,  Chia-Lin Yang ,  Ye-Jyun Lin ,  Cheng-Yuan Wang

IPC: G11C13/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0069

Abstract: A method for operating a memory includes receiving a command to program a data value at a memory cell, and an indication of which write mode in a plurality of write modes to use. Write modes in the plurality are characterized by different sets of resistance ranges that correspond to data values stored in the memory cell. The method includes executing a program operation according to the indicated one in the plurality of write modes to program the data value in the memory cell. The plurality of write modes includes a first write mode and a second write mode corresponding to shorter data retention than the first write mode. The first and second write modes are characterized by first and second sets of resistance ranges in the different sets of resistance ranges. The method includes periodically refreshing data values in memory cells storing data in the second write mode.

Abstract translation: 一种用于操作存储器的方法包括接收对存储器单元的数据值进行编程的命令以及使用多种写入模式中的哪个写入模式的指示。 多个中的写入模式的特征在于对应于存储在存储单元中的数据值的不同的电阻范围。 该方法包括根据多个写入模式中指示的一个执行程序操作，以对存储单元中的数据值进行编程。 多个写入模式包括对应于比第一写入模式更短的数据保持的第一写入模式和第二写入模式。 第一和第二写入模式的特征在于不同的电阻范围集中的第一组和第二组电阻范围。 该方法包括在存储第二写入模式的数据的存储单元中周期性地刷新数据值。