公开(公告)号：US20120321028A1

公开(公告)日：2012-12-20

申请号：US13493599

申请日：2012-06-11

申请人： Atsuhiko Koizumi ,  Tsuyoshi Masugi ,  Osamu Takizawa ,  Naoto Odagawa ,  Masataka Yanagisawa ,  Toshifumi Sato

发明人： Atsuhiko Koizumi ,  Tsuyoshi Masugi ,  Osamu Takizawa ,  Naoto Odagawa ,  Masataka Yanagisawa ,  Toshifumi Sato

IPC分类号： G21C17/00

CPC分类号： G21D3/001 ,  G21C17/10 ,  G21C17/108 ,  Y02E30/40

摘要： A TIP monitoring control equipment has: a process computer, a TIP control panel, and data transmitting unit. The process computer includes a operation input unit, a TIP scanning unit, a first TIP level data transmitting and receiving unit, and a TIP level data storage unit. To a first TIP level data transmitting and receiving unit, an LPRM level signal, an APRM level signal and TIP level data accumulated in the TIP control panel are input in synchronization with a TIP position signal. The TIP control panel includes a TIP driving control unit, a TIP level processing unit, a TIP position processing unit, a TIP level data accumulation unit and a second TIP level data transmitting and receiving unit. The second TIP level data transmitting and receiving unit transmits TIP level data accumulated in the TIP level data accumulation unit to the process computer via the data transmission unit.

摘要翻译： TIP监控控制设备具有：过程计算机，TIP控制面板和数据发送单元。 处理计算机包括操作输入单元，TIP扫描单元，第一TIP级数据发送和接收单元以及TIP级数据存储单元。 对于第一TIP级数据发送和接收单元，与TIP位置信号同步地输入在TIP控制面板中累积的LPRM电平信号，APRM电平信号和TIP电平数据。 TIP控制面板包括TIP驱动控制单元，TIP级处理单元，TIP位置处理单元，TIP级数据累积单元和第二TIP级数据发送和接收单元。 第二TIP级数据发送和接收单元经由数据传输单元将累积在TIP级数据累积单元中的TIP级数据发送到处理计算机。

公开(公告)号：US20120007634A1

公开(公告)日：2012-01-12

申请号：US12957991

申请日：2010-12-01

申请人： Masataka YANAGISAWA ,  Toshifumi Sato

发明人： Masataka YANAGISAWA ,  Toshifumi Sato

IPC分类号： H03K19/177

CPC分类号： G21C17/108 ,  G05B23/0213 ,  G05B2219/21109 ,  G21D3/008 ,  Y02E30/40

摘要： According to an embodiment, a digital process type monitor device includes a plurality of modules and a mother board connected to each of the modules. Each module includes: a base board connected to a connector and having an FPGA for main control and an IPGA for sub board control mounted thereon; and a sub board for a main-machine I/F process, having an FPGA for an I/F process mounted hereon. Each sub board has storage devices for storing man-machine I/F information on the sub board. Each of the FPGA writes transmission data into a predetermined region of a transmission area and has a common transmission protocol to share the transmission data between the respective modules.

摘要翻译： 根据实施例，数字处理型监视器装置包括多个模块和连接到每个模块的母板。 每个模块包括：连接到连接器的基板，具有用于主控制的FPGA和安装在其上的用于子板控制的IPGA; 以及用于主机I / F处理的子板，其具有安装在其上的I / F处理的FPGA。 每个子板具有用于在子板上存储人机I / F信息的存储装置。 每个FPGA将传输数据写入到传输区域的预定区域中，并且具有共同的传输协议以共享各个模块之间的传输数据。

公开(公告)号：US09305670B2

公开(公告)日：2016-04-05

申请号：US13493599

申请日：2012-06-11

申请人： Atsuhiko Koizumi ,  Tsuyoshi Masugi ,  Osamu Takizawa ,  Naoto Odagawa ,  Masataka Yanagisawa ,  Toshifumi Sato

发明人： Atsuhiko Koizumi ,  Tsuyoshi Masugi ,  Osamu Takizawa ,  Naoto Odagawa ,  Masataka Yanagisawa ,  Toshifumi Sato

IPC分类号： G21C17/00 ,  G21D3/00 ,  G21C17/108 ,  G21C17/10

CPC分类号： G21D3/001 ,  G21C17/10 ,  G21C17/108 ,  Y02E30/40

摘要： A TIP monitoring control equipment has: a process computer, a TIP control panel, and data transmitting unit. The process computer includes a operation input unit, a TIP scanning unit, a first TIP level data transmitting and receiving unit, and a TIP level data storage unit. To a first TIP level data transmitting and receiving unit, an LPRM level signal, an APRM level signal and TIP level data accumulated in the TIP control panel are input in synchronization with a TIP position signal. The TIP control panel includes a TIP driving control unit, a TIP level processing unit, a TIP position processing unit, a TIP level data accumulation unit and a second TIP level data transmitting and receiving unit. The second TIP level data transmitting and receiving unit transmits TIP level data accumulated in the TIP level data accumulation unit to the process computer via the data transmission unit.

摘要翻译： TIP监控控制设备具有：过程计算机，TIP控制面板和数据发送单元。 处理计算机包括操作输入单元，TIP扫描单元，第一TIP级数据发送和接收单元以及TIP级数据存储单元。 对于第一TIP级数据发送和接收单元，与TIP位置信号同步地输入在TIP控制面板中累积的LPRM电平信号，APRM电平信号和TIP电平数据。 TIP控制面板包括TIP驱动控制单元，TIP级处理单元，TIP位置处理单元，TIP级数据累积单元和第二TIP级数据发送和接收单元。 第二TIP级数据发送和接收单元经由数据传输单元将累积在TIP级数据累积单元中的TIP级数据发送到处理计算机。

公开(公告)号：US08331521B2

公开(公告)日：2012-12-11

申请号：US12957991

申请日：2010-12-01

申请人： Masataka Yanagisawa ,  Toshifumi Sato

发明人： Masataka Yanagisawa ,  Toshifumi Sato

IPC分类号： G21C17/10

CPC分类号： G21C17/108 ,  G05B23/0213 ,  G05B2219/21109 ,  G21D3/008 ,  Y02E30/40

摘要： According to an embodiment, a digital process type monitor device includes a plurality of modules and a mother board connected to each of the modules. Each module includes: a base board connected to a connector and having an FPGA for main control and an IPGA for sub board control mounted thereon; and a sub board for a main-machine I/F process, having an FPGA for an I/F process mounted hereon. Each sub board has storage devices for storing man-machine I/F information on the sub board. Each of the FPGA writes transmission data into a predetermined region of a transmission area and has a common transmission protocol to share the transmission data between the respective modules.

摘要翻译： 根据实施例，数字处理型监视器装置包括多个模块和连接到每个模块的母板。 每个模块包括：连接到连接器的基板，具有用于主控制的FPGA和安装在其上的用于子板控制的IPGA; 以及用于主机I / F处理的子板，其具有安装在其上的I / F处理的FPGA。 每个子板具有用于在子板上存储人机I / F信息的存储装置。 每个FPGA将传输数据写入到传输区域的预定区域中，并且具有共同的传输协议以共享各个模块之间的传输数据。

公开(公告)号：US09271272B2

公开(公告)日：2016-02-23

申请号：US13818294

申请日：2012-07-25

申请人： Yassin Aden Awad ,  Yasushi Maruta ,  Toshifumi Sato

发明人： Yassin Aden Awad ,  Yasushi Maruta ,  Toshifumi Sato

IPC分类号： H04W72/04 ,  H04W16/28

CPC分类号： H04W72/042 ,  H04W16/28 ,  H04W72/0406 ,  H04W72/0453 ,  H04W72/046

摘要： A communication system is presented in which a base station is provided for communicating with a plurality of mobile communication devices in a cellular communication system. The base station operates one of more communication cells and communicates subframes, with each of the plurality of communication devices within the cell(s), each comprising the communication resources of a control region for communicating a control channel and the communication resources of a data region for communicating a respective data channel. The base station communicates a control channel having a first DMRS sequence in a control region of some subframes and a control channel having a second DMRS sequence in a control region of other subframes. The second control channel may be transmitted in a radio beam focussed spatially in a direction of a communication device. The first control channel may be transmitted omnidirectionally throughout the cell(s).

摘要翻译： 提出了一种通信系统，其中提供基站用于在蜂窝通信系统中与多个移动通信设备进行通信。 基站操作多个通信小区中的一个，并且与小区内的多个通信设备中的每一个通信子帧，每个通信单元包括用于传送控制信道的控制区域的通信资源和数据区域的通信资源 用于传送相应的数据信道。 基站在一些子帧的控制区域中传送具有第一DMRS序列的控制信道和在其他子帧的控制区域中具有第二DMRS序列的控制信道。 第二控制信道可以在通信设备的空间上聚焦的无线电波束中发送。 第一控制信道可以在整个小区中全向传输。

公开(公告)号：US08804769B2

公开(公告)日：2014-08-12

申请号：US12736061

申请日：2009-03-03

申请人： Hiroki Tanaka ,  Motoya Iwasaki ,  Toshifumi Sato ,  Yoshitsugu Shimazu ,  Atsushi Tsuyuki

发明人： Hiroki Tanaka ,  Motoya Iwasaki ,  Toshifumi Sato ,  Yoshitsugu Shimazu ,  Atsushi Tsuyuki

IPC分类号： H04J3/06

CPC分类号： H04J3/0685 ,  H04J3/047 ,  H04L7/0029

摘要： A multiplexing/demultiplexing device has a phase difference detection part for detecting a phase difference from a reference frequency of a multiplexed signal and a reference frequency of each of input/output lines, an interpolation part for performing an interpolation on a digital transmitting/receiving signal of each of the input/output lines with a signal delayed by time corresponding to the phase difference for each of the input/output lines based on the phase difference detected by the phase difference detection part to obtain a digital transmitting/receiving signal sampled with the reference frequency of the multiplexed signal for each of the input/output lines, and a signal multiplexing/demultiplexing part for performing a multiplex/demultiplex of the digital transmitting/receiving signals of the input/output lines with use of the reference frequency of the multiplexed signal.

摘要翻译： 复用/解复用装置具有相位差检测部分，用于检测与复用信号的参考频率和每个输入/输出线的参考频率的相位差，用于在数字发送/接收信号上执行内插的内插部分 基于由相位差检测部检测出的相位差，输入/输出线路中的每一个具有与每个输入/输出线路的相位差相对应的时间延迟的信号，以获得采用该相位差采样的数字发送/接收信号 用于每个输入/输出线路的复用信号的参考频率，以及信号复用/解复用部分，用于使用多路复用的参考频率来执行输入/输出线路的数字发送/接收信号的复用/解复用 信号。

公开(公告)号：US20110002247A1

公开(公告)日：2011-01-06

申请号：US12736061

申请日：2009-03-03

申请人： Hiroki Tanaka ,  Motoya Iwasaki ,  Toshifumi Sato ,  Atsushi Tsuyuki

发明人： Hiroki Tanaka ,  Motoya Iwasaki ,  Toshifumi Sato ,  Atsushi Tsuyuki

IPC分类号： H04B7/00 ,  H04J3/06 ,  H04J1/00

CPC分类号： H04J3/0685 ,  H04J3/047 ,  H04L7/0029

摘要： A multiplexing/demultiplexing device has a phase difference detection part for detecting a phase difference from a reference frequency of a multiplexed signal and a reference frequency of each of input/output lines, an interpolation part for performing an interpolation on a digital transmitting/receiving signal of each of the input/output lines with a signal delayed by time corresponding to the phase difference for each of the input/output lines based on the phase difference detected by the phase difference detection part to obtain a digital transmitting/receiving signal sampled with the reference frequency of the multiplexed signal for each of the input/output lines, and a signal multiplexing/demultiplexing part for performing a multiplex/demultiplex of the digital transmitting/receiving signals of the input/output lines with use of the reference frequency of the multiplexed signal.

摘要翻译： 复用/解复用装置具有相位差检测部分，用于检测与复用信号的参考频率和每个输入/输出线的参考频率的相位差，用于在数字发送/接收信号上执行内插的内插部分 基于由相位差检测部检测出的相位差，输入/输出线路中的每一个具有与每个输入/输出线路的相位差相对应的时间延迟的信号，以获得采用该相位差采样的数字发送/接收信号 用于每个输入/输出线路的复用信号的参考频率，以及信号复用/解复用部分，用于使用多路复用的参考频率来执行输入/输出线路的数字发送/接收信号的复用/解复用 信号。

公开(公告)号：US07609679B2

公开(公告)日：2009-10-27

申请号：US10970276

申请日：2004-10-22

申请人： Toshifumi Sato

发明人： Toshifumi Sato

IPC分类号： H04B7/216 ,  H03C7/02

CPC分类号： H04B7/2637

摘要： A cellular system using a code division multiple access (CDMA) scheme includes N (N is a positive integer) pilot channels and M (M is a positive integer) data channels. The pilot channels are used transmitting reference signals whose transmission signals are known in advance. The data channels are used for transmitting information. Each of the M data channels is made to correspond to one or a plurality of said N pilot channels.

摘要翻译： 使用码分多址（CDMA）方案的蜂窝系统包括N（N是正整数）导频信道，M（M是正整数）数据信道。 导频信道用于传输信号是预先已知的参考信号。 数据通道用于传输信息。 使M个数据信道中的每一个对应于一个或多个所述N个导频信道。

公开(公告)号：US20090164955A1

公开(公告)日：2009-06-25

申请号：US12372518

申请日：2009-02-17

申请人： Mikio Izumi ,  Toshifumi Hayashi ,  Shigeru Odanaka ,  Hirotaka Sakai ,  Naotaka Oda ,  Toshifumi Sato ,  Toshiaki Ito

发明人： Mikio Izumi ,  Toshifumi Hayashi ,  Shigeru Odanaka ,  Hirotaka Sakai ,  Naotaka Oda ,  Toshifumi Sato ,  Toshiaki Ito

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device.

摘要翻译： 提供了一种用于验证包括具有多个功能元件的可编程逻辑器件的安全装置的验证方法。 验证方法包括以下步骤：在实际硬件上彻底验证多个功能元件，生成与使用预定的硬件描述语言在实际装置上验证的功能元件中的一个功能元件相同的功能元件，独立地逻辑合成每个产生的功能元件 功能元件组合成多个第一网络列表，使用预定的硬件描述语言在功能元件之间生成连接功能，将生成的连接功能逻辑合成到与连接功能相对应的第二网络列表中，将第一网络列表与 第二网络列表以产生第三网络列表，基于第三网络列表将逻辑电路写入可编程逻辑设备，以及验证实际的可编程逻辑设备。

公开(公告)号：US20090052427A1

公开(公告)日：2009-02-26

申请号：US12278694

申请日：2007-02-07

申请人： Kengo Oketani ,  Yoshikazu Kakura ,  Toshifumi Sato ,  Shousei Yoshida

发明人： Kengo Oketani ,  Yoshikazu Kakura ,  Toshifumi Sato ,  Shousei Yoshida

IPC分类号： H04B7/212

CPC分类号： H04L5/0048 ,  H04L5/0007 ,  H04L25/022 ,  H04L25/03159 ,  H04L27/2601 ,  H04L27/261 ,  H04W28/06 ,  H04W88/00

摘要： A memory 21 of a pilot processing circuit 2 holds in advance a pilot sequence converted into a frequency region signal obtained by subjecting a pilot signal symbol transmitted in one block to Ntx_p-point DFT. The pilot sequence held in the memory 21 is subjected to a series of processes including a roll-off filtering by a roll-off filter circuit 22, subcarrier mapping process by subcarrier mapping circuit 23, an Ndft_p-point IDFT operation by an IDFT circuit 24, and a cyclic prefix adding process by a cyclic prefix adding circuit 25.

摘要翻译： 导频处理电路2的存储器21预先保存转换成通过对在一个块中发送的导频信号符号进行Ntx_p点DFT而获得的频域信号的导频序列。 保存在存储器21中的导频序列经过一系列处理，包括滚降滤波器电路22的滚降滤波，副载波映射电路23的子载波映射处理，IDFT电路24的Ndft_p点IDFT操作 ，以及循环前缀添加电路25的循环前缀添加处理。