公开(公告)号：US06806097B2

公开(公告)日：2004-10-19

申请号：US10669072

申请日：2003-09-23

申请人： Matthias Kroenke ,  Igor Kasko

发明人： Matthias Kroenke ,  Igor Kasko

IPC分类号： H01L2100

CPC分类号： H01L21/76855 ,  H01L21/7687 ,  H01L21/76888 ,  H01L28/55 ,  H01L28/75

摘要： Ferroelectric memory cells are produced according to the stack principle. An adhesive layer is formed between a capacitor electrode of a memory capacitor and a conductive plug. An oxygen diffusion barrier is formed above the adhesive layer and once the ferroelectric has been deposited, the adhesive layer and the barrier are subjected to rapid thermal processing (RTP) in an oxygen atmosphere. An oxygen rate of the adhesive layer and the diffusion coefficient of oxygen in the material of the adhesive layer dependent on the temperature are determined. A diffusion coefficient of silicon in the material of the adhesive layer, dependent on the temperature, is determined. A temperature range for the RTP step from the two diffusion coefficients, determined for a predetermined layer thickness and layer width of the adhesive layer and the oxygen diffusion barrier is calculated, therefore, the siliconization of the adhesive layer occurs more rapidly than its oxidation.

摘要翻译： 铁电存储单元根据堆叠原理生产。 在记忆电容器的电容器电极和导电插塞之间形成粘合剂层。 在粘合剂层的上方形成氧扩散阻挡层，一旦沉积了铁电体，则在氧气氛中对粘合剂层和阻挡层进行快速热处理（RTP）。 确定粘合剂层的氧气速率和取决于温度的粘合剂层的材料中的氧的扩散系数。 确定粘合剂层材料中硅的扩散系数，取决于温度。 计算出从预定层厚度和粘合剂层的层宽度以及氧扩散阻挡层确定的两个扩散系数的RTP步骤的温度范围，因此粘合层的硅化比其氧化发生得更快。

公开(公告)号：US06875652B2

公开(公告)日：2005-04-05

申请号：US10638594

申请日：2003-08-11

申请人： Igor Kasko ,  Matthias Kroenke ,  Thomas Mikolajick

发明人： Igor Kasko ,  Matthias Kroenke ,  Thomas Mikolajick

IPC分类号： H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/8244

CPC分类号： H01L21/7687 ,  H01L21/76888 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

摘要： The invention relates to a method for producing ferroelectric capacitors that are structured using the stack principle and that are used in integrated semiconductor memory chips. The individual capacitor modules have an oxygen barrier between a lower capacitor electrode and an electrically conductive plug. At a site where it is not covered by the corresponding oxygen barrier, an unstructured adhesive layer is oxidized by the oxygen arising during the tempering process of the ferroelectric and forms insulating segments at the site in such a way that the lower capacitor electrodes of the ferroelectric capacitors are electrically insulated from one another. This makes it possible to dispense with structuring the adhesive layer. Furthermore, the layer serves as a getter of oxygen and inhibits the diffusion of oxygen to the plug.

摘要翻译： 本发明涉及一种用于制造铁电电容器的方法，所述铁电电容器使用堆叠原理构造并且用于集成半导体存储器芯片。 各个电容器模块在下部电容器电极和导电插塞之间具有氧气阻挡层。 在不被相应氧气阻挡层覆盖的位置处，非结构化粘合剂层被铁电体的回火过程中产生的氧氧化，并且在现场形成绝缘段，使得铁电体的下电容器电极 电容器彼此电绝缘。 这使得可以省略结构化粘合剂层。 此外，该层用作氧气的吸气剂并且抑制氧扩散到塞子。

公开(公告)号：US20070059892A1

公开(公告)日：2007-03-15

申请号：US11513835

申请日：2006-08-31

申请人： Matthias Kroenke ,  Dirk Offenberg

发明人： Matthias Kroenke ,  Dirk Offenberg

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L27/10873 ,  H01L27/10894

摘要： A semiconductor structure is fabricated to have a transistor cell region and a connection region. The transistors both of a transistor cell region and of a connection region are coated with a first oxide layer, the layer thickness of the first oxide layer being dimensioned in such a way that a gap region in each case remains present between the adjacent transistors in the transistor cell region. A sacrificial structure is subsequently applied between at least two adjacent transistors of the transistor cell region in the gap region. At least one gap region in each case remains free between two adjacent sacrificial structures. A second oxide layer is applied to the sacrificial structures and the first oxide layer. The first and second oxide layers are subjected to an etching step in which at least one spacer having a predetermined spacer width is formed on the side edges of at least one transistor of the connection region, the spacer being formed by the first and second oxide layers and the spacer width being determined by the layer thickness of the first and second oxide layers and also by the etching step.

摘要翻译： 制造半导体结构以具有晶体管单元区域和连接区域。 晶体管单元区域和连接区域的晶体管都涂覆有第一氧化物层，第一氧化物层的层厚度的尺寸使得每种情况下的间隙区域保持在相邻晶体管之间的间隙区域中 晶体管单元区域。 随后在间隙区域中的晶体管单元区域的至少两个相邻晶体管之间施加牺牲结构。 在每种情况下，至少一个间隙区域在两个相邻的牺牲结构之间保持自由。 第二氧化物层被施加到牺牲结构和第一氧化物层。 对第一氧化物层和第二氧化物层进行蚀刻步骤，其中在连接区域的至少一个晶体管的侧边缘上形成具有预定间隔物宽度的至少一个间隔物，间隔物由第一和第二氧化物层形成 并且间隔物宽度由第一和第二氧化物层的层厚度以及蚀刻步骤决定。

公开(公告)号：US20060172539A1

公开(公告)日：2006-08-03

申请号：US11043950

申请日：2005-01-28

申请人： Matthias Kroenke ,  Thomas Dittkrist ,  Werner Graf

发明人： Matthias Kroenke ,  Thomas Dittkrist ,  Werner Graf

IPC分类号： H01L21/302

CPC分类号： H01L21/31053

摘要： The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A plurality of layers is deposited on said surface wherein a lower layer exhibits a higher polishing rate than an upper layer and wherein the thickness of the plurality of layers exceeds the step height. Afterwards the plurality of layers is chemically mechanically polished such that the lower layer is at least partly removed in the first region. By this method achieves a better planarisation. Additionally, smaller top contact openings after a wet clean step are achievable and a deformation of contact openings due to annealing steps is reduced.

摘要翻译： 本发明提供了一种处理结构化表面的简单方法，该结构化表面包括在第二区域中的第一区域和下表面中的较高表面。 多个层沉积在所述表面上，其中下层表现出比上层更高的抛光速率，并且其中多个层的厚度超过台阶高度。 之后，多层被化学机械抛光，使得下层在第一区域中被至少部分去除。 通过这种方法实现更好的平面化。 此外，可以实现在湿式清洁步骤之后较小的顶部接触开口，并且由于退火步骤导致的接触开口的变形减小。

公开(公告)号：US06984578B2

公开(公告)日：2006-01-10

申请号：US10476355

申请日：2002-04-11

申请人： Wolfgang Gustin ,  Kae-Horng Wang ,  Matthias Kroenke

发明人： Wolfgang Gustin ,  Kae-Horng Wang ,  Matthias Kroenke

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76816 ,  H01L27/115 ,  H01L27/11521

摘要： The invention relates to a method for the production of an integrated circuit, comprising the following steps: a substrate (1) is provided with at least one first, second and third gate stack (GS1, GS2, GS3) of approximately the same height surface of said substrate, a common active area (60) being provided on the surface of the substrate in said substrate (1) between the first and second gate stack (GS1, GS2); a first insulating layer (70) is provided in order to cover the embedding of the first second and third gate stack (GS1, GS2, GS3); the upper side of a gate connection (20) of the third gate stack (GS3) is uncovered; a second insulating layer (80) is provided in order to cover the upper side of a gate connection (20); a mask (M2) is provided on the resulting structure having a first opening (12a) above the uncovered upper side of the gate connection (20) of the third gate stack (GS3), a second opening (F2b) above the substrate (1) between the third and second gate stack (GS3, GS2) and a third opening (F2c) above the common active area (60), partially overlapping the first and second gate stack (GS1, GS2), and simultaneously forming a first, second and third contact hole (KB, KS, KG) using said mask (32) in an etching process, the first contact hole (KB) uncovering the common active area (60) on the surface of the substrate between the first and second gate stack (GS1, GS2), the second contact hole (KS) uncovering the surface of the substrate between the second and third gate stack (GS2, GS2) and the third contact hole (KG) uncovering the upper side of the gate connection (20) of the third gate stack (GS3).

摘要翻译： 本发明涉及一种用于生产集成电路的方法，包括以下步骤：衬底（1）设置有至少一个第一，第二和第三栅堆叠（GS 1，GS 2，GS 3） 所述衬底的相同高度表面，在第一和第二栅极堆叠（GS 1，GS 2）之间的所述衬底（1）的衬底的表面上设置公共有源区（60）; 提供第一绝缘层（70）以覆盖第一第二和第三栅极堆叠（GS 1，GS 2，GS 3）的嵌入; 第三栅极堆叠（GS 3）的栅极连接（20）的上侧未被覆盖; 设置第二绝缘层（80）以覆盖栅极连接（20）的上侧; 在所得到的结构上设置掩模（M 2），其具有在第三栅极堆叠（GS 3）的栅极连接（20）的未覆盖的上侧上方的第一开口（12a），第二开口（F2b） 在第三和第二栅极堆叠（GS 3，GS 2）之间的衬底（1）上方和公共有效区域（60）上方的第三开口（F 2 c）之上，部分地与第一和第二栅极堆叠（GS1， GS 2），并且在蚀刻工艺中使用所述掩模（32）同时形成第一，第二和第三接触孔（KB，KS，KG），所述第一接触孔（KB）露出所述公共有效区域 在第一和第二栅极堆叠（GS1，GS2）之间的衬底表面，第二接触孔（KS）露出第二和第三栅极堆叠（GS 2，GS 2）和第三接触之间的衬底表面 孔（KG）露出第三栅极堆叠（GS3）的栅极连接（20）的上侧。

公开(公告)号：US07208416B2

公开(公告)日：2007-04-24

申请号：US11043950

申请日：2005-01-28

申请人： Matthias Kroenke ,  Thomas Dittkrist ,  Werner Graf

发明人： Matthias Kroenke ,  Thomas Dittkrist ,  Werner Graf

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/31 ,  H01L21/469 ,  H01L21/44

CPC分类号： H01L21/31053

摘要： The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A plurality of layers is deposited on said surface wherein a lower layer exhibits a higher polishing rate than an upper layer and wherein the thickness of the plurality of layers exceeds the step height. Afterwards the plurality of layers is chemically mechanically polished such that the lower layer is at least partly removed in the first region. By this method achieves a better planarization. Additionally, smaller top contact openings after a wet clean step are achievable and a deformation of contact openings due to annealing steps is reduced.

摘要翻译： 本发明提供了一种处理结构化表面的简单方法，该结构化表面包括在第二区域中的第一区域和下表面中的较高表面。 多个层沉积在所述表面上，其中下层表现出比上层更高的抛光速率，并且其中多个层的厚度超过台阶高度。 之后，多层被化学机械抛光，使得下层在第一区域中被至少部分去除。 通过该方法实现更好的平面化。 此外，可以实现在湿式清洁步骤之后较小的顶部接触开口，并且由于退火步骤导致的接触开口的变形减小。