公开(公告)号：US20180142577A1

公开(公告)日：2018-05-24

申请号：US15568685

申请日：2016-04-19

Applicant: Peter ORTMANN ,  Werner GRAF

Inventor： Peter ORTMANN ,  Werner GRAF

IPC: F01K3/00 ,  F01K25/00 ,  F01K3/06 ,  F01K3/12

CPC classification number: F01K3/006 ,  F01K3/06 ,  F01K3/12 ,  F01K25/00 ,  F01K25/005

Abstract: An energy storage device for storing energy including: a high-temperature regenerator containing a storage material and a working gas as heat transfer medium for the purpose of exchanging heat between the storage material and the traversing working gas, a closed charging circuit for the working gas, including a first compressor, a first expander, a first recuperator having a first and a second heat exchange duct, the high-temperature regenerator and a pre-heater, wherein the first compressor is coupled to the first expander by a shaft, a discharging circuit for the working gas, and including a switch that selectively connects the high-temperature regenerator to either the charging circuit or the discharging circuit, such that the circuit containing the high-temperature regenerator forms a closed circuit.

公开(公告)号：US07361974B2

公开(公告)日：2008-04-22

申请号：US11388234

申请日：2006-03-23

Applicant: Werner Graf

Inventor： Werner Graf

IPC: H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76829 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888 ,  H01L27/10894

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a sacrificial plug made of a first material surrounded by an isolation layer between two adjacent gate stacks in the first region; depositing a planarisation layer over said plurality of gate stacks in said first region and said at least one gate stack in said second region; backpolishing said planarisation layer such that the upper surface of said sacrificial plug is exposed; forming a structured hardmask layer made of said first material on said backpolished planarisation layer which structured hardmask layer adjoins said sacrificial plug and has at least one opening in said second region; forming at least one contact hole in said second region under said at least one opening in said second region, said at least one contact hole exposing a substrate contact area adjacent to said gate stack in said second region or a contact area in said gate stack; selectively removing said hardmask layer and said sacrificial plug in a single etch step, whereby another contact hole is formed between two adjacent gate stacks in said first region; removing said isolation layer on the bottom of said another contact hole such that the substrate is exposed; and filling said contact hole and said another contact hole with a respective contact plug.

Abstract translation: 本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：提供在第一区域中具有多个栅极叠层的半导体衬底和在第二区域中的至少一个栅极叠层; 形成由在所述第一区域中的两个相邻栅极叠层之间的隔离层围绕的第一材料制成的牺牲插塞; 在所述第一区域中的所述多个栅极堆叠上沉积平面化层，并且在所述第二区域中沉积所述至少一个栅极堆叠; 抛光所述平面化层，使得所述牺牲塞的上表面露出; 在所述后抛光平面化层上形成由所述第一材料制成的结构化硬掩模层，所述结构化硬掩模层与所述牺牲塞邻接，并且在所述第二区域中具有至少一个开口; 在所述第二区域的所述至少一个开口下方的所述第二区域内形成至少一个接触孔，所述至少一个接触孔暴露在所述第二区域中的所述栅极堆叠附近的衬底接触区域或所述栅极叠层中的接触区域; 在单个蚀刻步骤中选择性地去除所述硬掩模层和所述牺牲塞，由此在所述第一区域中的两个相邻的栅叠层之间形成另一个接触孔; 去除所述另一个接触孔的底部上的所述隔离层，使得所述衬底露出; 以及用相应的接触插塞填充所述接触孔和所述另一个接触孔。

公开(公告)号：US20070224810A1

公开(公告)日：2007-09-27

申请号：US11388234

申请日：2006-03-23

Applicant: Werner Graf

Inventor： Werner Graf

IPC: H01L21/44

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76829 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888 ,  H01L27/10894

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a sacrificial plug made of a first material surrounded by an isolation layer between two adjacent gate stacks in the first region; depositing a polarization layer over said plurality of gate stacks in said first region and said at least one gate stack in said second region; backpolishing said polarization layer such that the upper surface of said sacrificial plug is exposed; forming a structured hardmask layer made of said first material on said backpolished polarization layer which structured hardmask layer adjoins said sacrificial plug and has at least one opening in said second region; forming at least one contact hole in said second region under said at least one opening in said second region, said at least one contact hole exposing a substrate contact area adjacent to said gate stack in said second region or a contact area in said gate stack; selectively removing said hardmask layer and said sacrificial plug in a single etch step, whereby another contact hole is formed between two adjacent gate stacks in said first region; removing said isolation layer on the bottom of said another contact hole such that the substrate is exposed; and filling said contact hole and said another contact hole with a respective contact plug.

Abstract translation: 本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：提供在第一区域中具有多个栅极叠层的半导体衬底和在第二区域中的至少一个栅极叠层; 形成由在所述第一区域中的两个相邻栅极叠层之间的隔离层围绕的第一材料制成的牺牲插塞; 在所述第一区域中的所述多个栅极堆叠上沉积偏振层，并在所述第二区域中沉积所述至少一个栅极堆叠; 反向抛光所述偏振层，使得所述牺牲塞的上表面露出; 在所述后抛光偏振层上形成由所述第一材料制成的结构化硬掩模层，所述结构化硬掩模层与所述牺牲插塞相邻，并且在所述第二区域中具有至少一个开口; 在所述第二区域的所述至少一个开口下方的所述第二区域内形成至少一个接触孔，所述至少一个接触孔暴露在所述第二区域中的所述栅极堆叠附近的衬底接触区域或所述栅极叠层中的接触区域; 在单个蚀刻步骤中选择性地去除所述硬掩模层和所述牺牲塞，由此在所述第一区域中的两个相邻的栅叠层之间形成另一个接触孔; 去除所述另一个接触孔的底部上的所述隔离层，使得所述衬底露出; 以及用相应的接触插塞填充所述接触孔和所述另一个接触孔。

公开(公告)号：US07094674B2

公开(公告)日：2006-08-22

申请号：US10739477

申请日：2003-12-18

Applicant: Werner Graf ,  Henning Haffner ,  Johannes Kowalewski ,  Lars Heineck

Inventor： Werner Graf ,  Henning Haffner ,  Johannes Kowalewski ,  Lars Heineck

IPC: H01L21/44

CPC classification number: H01L27/10888 ,  H01L21/76897

Abstract: The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved in that a strip structure extending over two layers is used to structure the contacts. The strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in the mutually overlapping areas of the strip structures in the two layers.

公开(公告)号：US20060148227A1

公开(公告)日：2006-07-06

申请号：US11115385

申请日：2005-04-27

Applicant: Matthias Kronke ,  Joachim Patzer ,  Werner Graf

Inventor： Matthias Kronke ,  Joachim Patzer ,  Werner Graf

IPC: H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76831 ,  H01L27/10888 ,  H01L27/10894

Abstract: A silicon dioxide layer is formed and a mask layer is deposited and then patterned to produce openings in the mask layer in the region around the gate contacts onto the gate electrode tracks in the logic region. The surface is uncovered around the gate contacts to the gate electrode tracks in the logic region, reducing the silicon dioxide layer. A sacrificial layer covering the gate electrode tracks is formed and patterned to form sacrificial layer blocks above the contact openings for the bit line contacts between the mutually adjacent gate electrode tracks in the cell array region and above the contact openings for the substrate contacts to the semiconductor surface and the gate contacts onto the gate electrode tracks in the logic region. A filling layer is formed between the sacrificial layer blocks, and the sacrificial layer blocks are removed. The contact opening regions are filled with conductive material.

Abstract translation: 形成二氧化硅层，并且沉积掩模层，然后图案化以在栅极接触周围的区域中的掩模层中产生在逻辑区域中的栅电极轨道上的开口。 围绕逻辑区域中的栅极电极的栅极触点周围没有表面，减少了二氧化硅层。 覆盖栅极电极轨迹的牺牲层被形成并图案化以在接触开口上方形成用于电池阵列区域中相互相邻的栅极电极轨道之间的位线接触和用于衬底接触半导体的接触开口之上的位线接触的牺牲层块 表面，并且栅极接触逻辑区域中的栅极电极轨迹。 在牺牲层块之间形成填充层，去除牺牲层块。 接触开口区域填充有导电材料。

公开(公告)号：US20060141756A1

公开(公告)日：2006-06-29

申请号：US11282432

申请日：2005-11-18

Applicant: Werner Graf ,  Lars Heineck ,  Jana Horst

Inventor： Werner Graf ,  Lars Heineck ,  Jana Horst

IPC: H01L21/331 ,  H01L21/265

CPC classification number: H01L27/105 ,  H01L27/1052

Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

Abstract translation: 在制造半导体结构的方法中，提供了具有顶表面的衬底的半导体。 栅极电介质层设置在顶表面上，并且在栅极介电层上提供有具有第一多个栅极堆叠的存储单元阵列区域和具有第二多个栅极堆叠的外围元件区域。 在存储单元阵列区域和外围元件区域上提供介电层。 执行存储单元阵列区域和外围元件区域上的第一源极/漏极注入，形成存储单元阵列区域上的阻挡掩模，使用阻挡掩模去除电介质层，并且使用第二源极/漏极注入 在存储单元阵列区域和外围元件区域上进行，其中存储单元阵列区域被掩模保护。

公开(公告)号：US07018781B2

公开(公告)日：2006-03-28

申请号：US10811509

申请日：2004-03-29

Applicant: Hans-Georg Fröhlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

Inventor： Hans-Georg Fröhlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

IPC: G03F7/00

CPC classification number: H01L27/10888 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76897 ,  H01L27/10894

Abstract: Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.

Abstract translation: 公开了一种在具有选择晶体管的存储单元的布置的存储器模块中制造合同孔平面的方法。 可以在生产动态随机存取存储器（DRAM）模块期间利用这些方法。

公开(公告)号：US07009290B2

公开(公告)日：2006-03-07

申请号：US10487182

申请日：2002-12-05

Applicant: Uwe Bock ,  Werner Graf ,  Stephan Bock

Inventor： Uwe Bock ,  Werner Graf ,  Stephan Bock

IPC: H01L23/34 ,  H01L23/26 ,  F28F7/00 ,  H05K7/20

CPC classification number: H01L23/3672 ,  H01L21/4882 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heat sink for semiconductor components or similar devices, especially produced from an extruded aluminum alloy. The heat sink comprises cooling ribs which rise at a distance from a base plate and which are clamped in an insert groove made in the surface of the base plate, laterally limited by longitudinal or intermediate ribs with a coupling base that has an approximately rectangular cross-section. The coupling bases are held in their insert grooves in a form-fit and are cold-welded with the base plate at least in some sections. Cross ribs extend at a distance to one another on the surfaces of the intermediate ribs and have the form of upset heels that are linked with the coupling base in a form-fit.

Abstract translation: 用于半导体部件或类似装置的散热器，特别是由挤出的铝合金制成。 散热器包括冷却肋，其从基板延伸一定距离，并且夹紧在基板的表面中形成的插入槽中，横向由纵向或中间肋限制，连接座具有近似矩形横截面， 部分。 联接基座以形状配合保持在其插入槽中，并且至少在一些部分中与基板冷焊。 横肋在中间肋的表面上彼此间隔开一定距离，并且具有以与形状配合的联接基座连接的镦粗高跟的形式。

公开(公告)号：US5597882A

公开(公告)日：1997-01-28

申请号：US240742

申请日：1994-09-06

Applicant: August Schiller ,  Norman Dorsch ,  Werner Graf ,  Alois Strasser

Inventor： August Schiller ,  Norman Dorsch ,  Werner Graf ,  Alois Strasser

IPC: C07F7/22 ,  C08K5/544 ,  C08K5/57 ,  C08L83/04 ,  C08L83/14 ,  C08G77/06

CPC classification number: C08K5/57 ,  C07F7/2252 ,  C08L83/04 ,  C08G77/18 ,  C08G77/20 ,  C08G77/24

Abstract: The compositions proposed contain, as their main constituents,(a) a diorganopolysiloxane with triorganosiloxy groups as terminal groups, the organic groups being hydrocarbon groups which may be halogenated,(b) the reaction product of a diacylated diorganotin compound with a disilaalkane containing, per molecule, at least two monovalent hydrocarbon groups which are bonded to silicon via oxygen and may optionally be substituted by an alkoxy group, or with an oligomer of such a disilaalkane,(c) an organosilicon compound containing, per molecule, at least one amino or amino group bonded to silicon via carbon,(d) optionally, a filler and(e) optionally, a disilaalkane and/or silane containing, per molecule, at least three monovalent hydrocarbon groups which are bonded to silicon via oxygen and may optionally be substituted by an alkoxy group, or an oligomer of such a disilaalkane and/or silane.

Abstract translation: 所提出的组合物作为其主要成分包含（a）具有三有机甲硅烷氧基作为端基的二有机聚硅氧烷，有机基团可以被卤化的烃基，（b）二酰基二有机锡化合物与二硫代烷烃的反应产物 分子，至少两个通过氧连接到硅上并可任选地被烷氧基取代的单价烃基，或与二恶烷的低聚物结合的（c）每分子含有至少一个氨基或 氨基通过碳与硅键合，（d）任选的填料和（e）任选的二烷基和/或硅烷，每分子含有至少三个一价烃基，其通过氧连接到硅上，并且可以任选被取代 通过烷氧基，或这种二吡烷和/或硅烷的低聚物。

公开(公告)号：US5584518A

公开(公告)日：1996-12-17

申请号：US560430

申请日：1995-11-17

Applicant: Simon Frank ,  Werner Graf

Inventor： Simon Frank ,  Werner Graf

IPC: B60R19/18 ,  B60R19/24

CPC classification number: B60R19/24 ,  B60R2019/182

Abstract: A bumper with brackets attached for mounting it onto a vehicle, in particular a private car, is such that, at least in the region of the brackets, the bumper is bowed with respect to the front line of the vehicle, and features section walls a distance apart in the form of a compression wall and a tension wall and a pair of transverse walls joining them making up a hollow section. The brackets feature a wedge-shaped support, the sloping face of which lies against the tension wall and is connected to this in region at the highest point of the sloping face.

Abstract translation: 具有用于将其安装到车辆，特别是私家车上的支架的保险杠使得至少在支架的区域中，保险杠相对于车辆的前线弯曲，并且具有部分壁a 以压缩壁和张力壁的形式分开的距离和连接它们的一对横向壁组成中空部分。 支架具有楔形支撑件，其倾斜面抵靠张力壁，并且在倾斜面的最高点的区域连接到该支撑件。