公开(公告)号：US20230248982A1

公开(公告)日：2023-08-10

申请号：US18102367

申请日：2023-01-27

Applicant: Medtronic, Inc.

Inventor： Andrew J. Ries ,  Mark E. Henschel ,  James R. Wasson ,  Chunho Kim ,  Walter E. Benecke ,  Kris A. Peterson ,  Jeff M. Wheeler ,  Songhua Shi

IPC: A61N1/375 ,  A61N1/372

CPC classification number: A61N1/3754 ,  A61N1/37223

Abstract: Various embodiments of a feedthrough assembly are disclosed. The assembly includes a header and a test fanout layer electrically connected to the header. A first major surface of the test fanout layer faces an inner surface of the header. The assembly further includes a test via extending between the first major surface and a second major surface of the test fanout layer, and a test pad disposed on the first major surface of the test fanout layer and electrically connected to the test via. At least a portion of the test pad is disposed between the outer surface of the header and a perimeter of the test fanout layer as viewed in a plane parallel to the first major surface of the test fanout layer such that the at least a portion of the test pad is exposed.

公开(公告)号：US20230420383A1

公开(公告)日：2023-12-28

申请号：US17846601

申请日：2022-06-22

Applicant: Medtronic, Inc.

Inventor： Randolph E. Crutchfield ,  Jeff M. Wheeler

IPC: H01L23/552 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/552 ,  H01L23/528 ,  H01L21/76829 ,  H01L21/76895 ,  H01L23/5222

Abstract: Various embodiments of an integrated circuit package are disclosed. The package includes an integrated circuit having an integrated circuit contact disposed on a first major surface of the integrated circuit; a first passivation layer disposed on the first major surface of the integrated circuit and over the integrated circuit contact; and a redistribution layer disposed on the first passivation layer. The redistribution layer includes a conductive trace and a shield region that define a plane of the redistribution layer. The package further includes a second passivation layer disposed on the redistribution layer, and a patterned conductive layer disposed on the second passivation layer and including a conductive trace. A portion of the shield region of the redistribution layer is disposed between the conductive trace of the patterned conductive layer and the integrated circuit along an axis that is substantially orthogonal to the first major surface of the integrated circuit.