-
1.发明公开公开(公告)号：US20240231091A1
公开(公告)日：2024-07-11
申请号：US18410539
申请日：2024-01-11
Applicant: Meta Platforms Technologies, LLC
Inventor： Shrirang Madhav Yardi , Dinesh Patil , Neeraj Upasani
IPC: G02B27/01 , G06F1/3296 , G06T19/00
CPC classification number: G02B27/017 , G06F1/3296 , G06T19/006
Abstract: A system on a chip (SoC) comprises SoC memory; one or more processor subsystems, wherein each processor subsystem includes a processor connected to the SoC memory; and a low power subsystem integrated as a separate subsystem in the SoC, wherein the low power subsystem includes a microcontroller and a power management unit (PMU), wherein the microcontroller executes a real-time operating system (RTOS), wherein the PMU is connected to each processor subsystem, the PMU operating under the control of the microcontroller to control the power to each processor subsystem.
-
公开(公告)号：US20230252156A1
公开(公告)日：2023-08-10
申请号：US18296870
申请日：2023-04-06
Applicant: Meta Platforms Technologies, LLC
Inventor： Shrirang Madhav Yardi , Neeraj Upasani , Dinesh Patil
CPC classification number: G06F21/575 , G06F1/04 , G06F21/552 , G06F21/62 , G06F21/74 , G06F21/64 , G06F2221/034 , G06F3/011
Abstract: Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.
-
公开(公告)号：US20240231471A1
公开(公告)日：2024-07-11
申请号：US18410552
申请日：2024-01-11
Applicant: Meta Platforms Technologies, LLC
Inventor： Shrirang Madhav Yardi , Dinesh Patil , Neeraj Upasani
IPC: G06F1/3293
CPC classification number: G06F1/3293
Abstract: A system on a chip (SoC) comprises SoC memory; one or more processor subsystems, wherein each processor subsystem includes a processor connected to the SoC memory; and a low power subsystem integrated as a separate subsystem in the SoC, wherein the low power subsystem includes a microcontroller and a power management unit (PMU), wherein the microcontroller executes a real-time operating system (RTOS), wherein the PMU is connected to each processor subsystem, the PMU operating under the control of the microcontroller to control the power to each processor subsystem, wherein the low power subsystem is configured to boot up the SoC via the microcontroller executing out of SoC memory.
-
公开(公告)号：US11636210B2
公开(公告)日：2023-04-25
申请号：US17009512
申请日：2020-09-01
Applicant: Meta Platforms Technologies, LLC
Inventor： Shrirang Madhav Yardi , Neeraj Upasani , Dinesh Patil
IPC: G06F15/177 , G06F9/00 , G06F21/57 , G06F1/04 , G06F21/55 , G06F21/62 , G06F21/74 , G06F21/64 , G06F3/01
Abstract: Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.
-
公开(公告)号：US11601532B2
公开(公告)日：2023-03-07
申请号：US16860991
申请日：2020-04-28
Applicant: Meta Platforms Technologies, LLC
Inventor： Dinesh Patil , Wojciech Stefan Powiertowski , Neeraj Upasani , Sudhir Satpathy
IPC: H04L69/22 , H04L9/40 , H04B7/26 , H04L45/745 , G06F13/28 , G06F13/40 , G06F21/60 , G06F21/79 , H04W28/14
Abstract: In an example of the described techniques, a wireless communication system includes first memory, second memory, a first microcontroller, and a second microcontroller. The first microcontroller manages drivers for a wireless transceiver and direct data movement between the wireless transceiver and the first memory. The second microcontroller communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory. Additionally, the second microcontroller direct data movement between the second memory and the first memory.
-
Patent Agency Ranking
公开(公告)号：US11775448B2
公开(公告)日：2023-10-03
申请号：US18048302
申请日：2022-10-20
Applicant: Meta Platforms Technologies, LLC
Inventor： Sudhir Satpathy , Wojciech Stefan Powiertowski , Neeraj Upasani , Dinesh Patil
CPC classification number: G06F12/1408 , G02B27/017 , G06F12/1081 , G06F15/7807 , G06T19/006 , H04L63/0435
Abstract: This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.
-
公开(公告)号：US11637916B2
公开(公告)日：2023-04-25
申请号：US17457599
申请日：2021-12-03
Applicant: Meta Platforms Technologies, LLC
Inventor： Dinesh Patil , Wojciech Stefan Powiertowski , Neeraj Upasani , Sudhir Satpathy
IPC: G06F3/00 , H04L69/22 , H04L9/40 , H04B7/26 , H04L45/745 , G06F13/28 , G06F13/40 , G06F21/60 , G06F21/79 , H04W28/14
Abstract: The disclosure describes wireless communication systems. The wireless communication system includes first memory, second memory, a direct memory access (DMA) controller, an encryption engine in-line between the DMA controller and the second memory, a first microprocessor, and a second microprocessor. The first microprocessor communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory and programs the DMA controller to transfer packets of the application data to the first memory from the second memory. The encryption engine receives the packets of the application data from the DMA controller, encrypts the packets to generate encrypted application data packets, and outputs the encrypted application data packets for storage to the first memory.
-
公开(公告)号：US11520707B2
公开(公告)日：2022-12-06
申请号：US16694744
申请日：2019-11-25
Applicant: Meta Platforms Technologies, LLC
Inventor： Sudhir Satpathy , Wojciech Stefan Powiertowski , Neeraj Upasani , Dinesh Patil
Abstract: This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.
-
公开(公告)号：US11948654B1
公开(公告)日：2024-04-02
申请号：US17662178
申请日：2022-05-05
Applicant: Meta Platforms Technologies, LLC
Inventor： Shrirang Madhav Yardi , Dinesh Patil , Neeraj Upasani
CPC classification number: G11C29/4401 , G11C29/12005 , G11C29/36 , G11C29/46
Abstract: A system on a chip includes a first subsystem comprising a first memory; a second subsystem comprising a second memory; and an always-on subsystem. The always-on subsystem can comprise processing circuitry configured to: in response to a first activation event, signal the first subsystem to initiate repair operations on the first memory, and in response to a second activation event occurring after the first event, signal the second subsystem to initiate repair operations on the second memory.
-
公开(公告)号：US20230053821A1
公开(公告)日：2023-02-23
申请号：US18048302
申请日：2022-10-20
Applicant: Meta Platforms Technologies, LLC
Inventor： Sudhir Satpathy , Wojciech Stefan Powiertowski , Neeraj Upasani , Dinesh Patil
Abstract: This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.015 seconds)
