公开(公告)号：US5014059A

公开(公告)日：1991-05-07

申请号：US488185

申请日：1990-03-01

Applicant: Michael C. Seckora

Inventor： Michael C. Seckora

IPC: H03M1/12 ,  H03M1/66

CPC classification number: H03M1/662 ,  H03M1/1215

Abstract: A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into "n" CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of "n" elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.

Abstract translation: 串行到并行模拟CCD GaAs器件提供高速A / D或D / A转换。 通过将模拟数据串行地移动到“n”个CCD元件中，对高速模拟信号进行采样。 然后并行负载脉冲将模拟数据传输到多个CCD保持元件。 一组A / D转换器转换模拟数据。 相反，一组D / A转换器的输出并行加载到“n”个元件的串行CCD器件中。 串行CCD器件串行移出以完成转换为模拟信号。

公开(公告)号：US4906997A

公开(公告)日：1990-03-06

申请号：US206975

申请日：1988-06-13

Applicant: Michael C. Seckora

Inventor： Michael C. Seckora

IPC: H03M1/12 ,  H03M1/66

CPC classification number: H03M1/662 ,  H03M1/1215

Abstract: A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into "n" CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of "n" elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.

Abstract translation: 串行到并行模拟CCD GaAs器件提供高速A / D或D / A转换。 通过将模拟数据串行地移动到“n”个CCD元件中，对高速模拟信号进行采样。 然后并行负载脉冲将模拟数据传输到多个CCD保持元件。 一组A / D转换器转换模拟数据。 相反，一组D / A转换器的输出并行加载到“n”个元件的串行CCD器件中。 串行CCD器件串行移出以完成转换为模拟信号。

公开(公告)号：US07064278B2

公开(公告)日：2006-06-20

申请号：US10106977

申请日：2002-03-25

Applicant: Michael C. Seckora

Inventor： Michael C. Seckora

IPC: H05K1/16

CPC classification number: H05K1/0243 ,  H05K1/0231 ,  H05K3/305 ,  H05K3/3426 ,  H05K2201/09727 ,  H05K2201/10636 ,  H05K2201/10651 ,  H05K2201/10818 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49169

Abstract: Methods and apparatus provide for electrical coupling of electrical components to traces on a substrate such that impedance mismatches otherwise experienced in high frequency operation are avoided. Connecting elements having length, width, and thickness, are provided for terminals of a component to be connected to a trace. The connecting element is electrically coupled between the terminal and the trace, typically by soldering. The dimensions of the connecting element are chosen to reduce or eliminate the impedance mismatch which would result from a direct connection between the trace and component. Connecting elements are generally L-shaped, i.e., having first and second planar portions perpendicular with respect to each other, and having a curving portion that connects the first and second planar portions. In one embodiment, dimensions of at least a portion of the connecting element are such that its width increases as its distance from a ground plane within the substrate increases.

公开(公告)号：US5487023A

公开(公告)日：1996-01-23

申请号：US194963

申请日：1994-02-14

Applicant: Michael C. Seckora

Inventor： Michael C. Seckora

IPC: H03H17/02 ,  G06F17/10

CPC classification number: H03H17/0294

Abstract: A repeatable finite anti infinite impulse response integrated circuit structure has a plurality of filter units programmably interconnected, with each filter unit having a pair of repeatable cells. Each cell has a coefficient stage for receiving a filter coefficient, a mixer stage for multiplying a selected one of a plurality of input signals by the filter coefficient, an accumulator stage for selectively delaying an input accumulation signal, and a summation stage for adding the input accumulation signal to the weighted signal to produce an output accumulation signal. With appropriate programming many desired finite/infinite impulse response filter configurations may be achieved.

Abstract translation: 可重复的有限反无限脉冲响应集成电路结构具有可编程地互连的多个滤波器单元，每个滤波器单元具有一对可重复的单元。 每个单元具有用于接收滤波器系数的系数级，用于将多个输入信号中选择的一个乘以滤波器系数的混频器级，用于选择性地延迟输入累积信号的累加器级和用于将输入相加的求和级 累积信号到加权信号以产生输出累积信号。 通过适当的编程，可以实现许多期望的有限/无限脉冲响应滤波器配置。

公开(公告)号：US5465222A

公开(公告)日：1995-11-07

申请号：US195428

申请日：1994-02-14

Applicant: Michael C. Seckora

Inventor： Michael C. Seckora

IPC: G06F5/01 ,  G06F7/00 ,  G06F15/00

CPC classification number: G06F5/015

Abstract: A barrel shifter or multiply/divide integrated circuit (IC) structure includes a plurality of stages in series. The number of stages is a function of the number of bits in an input digital data word, and each stage in sequence provides for a different power of two rotary or multiply/divide shift of the digital data word at the input if selected. A multiplexer in each stage selects as an output either the shifted digital data word or the input digital data word for output to the next stage according to a shift amount select command. At the input and output of the series of stages an additional reversal multiplexer selects in response to a shift direction command either the digital data word or a reversed version of the digital data word, which determines the effective direction of the shift in the stages. Logic may be included in each stage to determine whether the shift operation is a rotary or multiply/divide shift operation.

Abstract translation: 桶形移位器或乘法/分频集成电路（IC）结构包括串联的多个级。 级数是输入数字数据字中的位数的函数，并且每个级按顺序提供如果选择的话，输入处的数字数据字的两次旋转或乘法/除法移位的不同功率。 每个级中的复用器根据移位量选择命令选择移位的数字数据字或输入数字数据字输出到下一级的输出。 在一系列级的输入和输出中，附加的反转多路复用器响应于数字数据字或数字数据字的反向版本的移位方向命令来选择，该数字数据字决定了级中的移位的有效方向。 可以在每个级中包括逻辑以确定换档操作是旋转还是乘法/除法换档操作。

公开(公告)号：US5214784A

公开(公告)日：1993-05-25

申请号：US276731

申请日：1988-11-28

Applicant: Benjamin A. Ward ,  Michael C. Seckora

Inventor： Benjamin A. Ward ,  Michael C. Seckora

IPC: G01R13/28 ,  G01R13/32 ,  G01R31/3177 ,  G06F11/25 ,  G06F11/28 ,  G06F11/34

CPC classification number: G06F11/348 ,  G01R31/3177 ,  G06F11/25 ,  G06F11/28

Abstract: A sequence of events detector provides a way to continuously monitor serial digital data and precisely define the behavior that it must exhibit in order to qualify as the sequence of events that the user wishes to detect. A plurality of evaluation windows each sequentially examine the behavior of one or more signals, comparing this behavior with predefined criteria. Each evaluation window is activated to begin its portion of the overall evaluation process by a match signal from the preceding window, indicating that its predefined criteria were met. In one version, a sequence starting circuit activates the first evaluation window in response to an external signal or the occurrence of a predefined condition, and a multiplexer trigger source circuit selects as the overall detector output the match signal output of the last evaluation window used to define the overall sequence of events. In another version, each evaluation window explicitly reports a failure if its predefined criteria are not met.

公开(公告)号：US4967198A

公开(公告)日：1990-10-30

申请号：US488207

申请日：1990-03-01

Applicant: Michael C. Seckora

Inventor： Michael C. Seckora

IPC: H03M1/12 ,  H03M1/66

CPC classification number: H03M1/662 ,  H03M1/1215

Abstract: A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into "n" CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of the "n" elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.

Abstract translation: 串行到并行模拟CCD GaAs器件提供高速A / D或D / A转换。 通过将模拟数据串行地移动到“n”个CCD元件中，对高速模拟信号进行采样。 然后并行负载脉冲将模拟数据传输到多个CCD保持元件。 一组A / D转换器转换模拟数据。 相反，一组D / A转换器的输出被并行加载到“n”个元件的串行CCD器件中。 串行CCD器件串行移出以完成转换为模拟信号。