公开(公告)号：US11769719B2

公开(公告)日：2023-09-26

申请号：US16017671

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Jonathan Rosch ,  Wei-Lun Jen ,  Cheng Xu ,  Liwei Cheng ,  Andrew Brown ,  Yikang Deng

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/111 ,  H05K1/115 ,  H05K1/025 ,  H05K1/18 ,  H05K2201/095 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09827

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US11765813B2

公开(公告)日：2023-09-19

申请号：US17359801

申请日：2021-06-28

Applicant: Amphenol Corporation

Inventor： Marc Robert Charbonneau ,  Jose Ricardo Paniagua

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/10 ,  H05K3/32 ,  H05K3/40 ,  H05K3/42 ,  H05K1/11

CPC classification number: H05K1/0225 ,  H05K1/0219 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/0723 ,  H05K2201/096 ,  H05K2201/09727 ,  H05K2201/09845

Abstract: A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers, the conductive layers including a signal layer; and via patterns formed in the plurality of layers, each of the via patterns comprising first and second signal vias extending from a first surface of the printed circuit board to the signal layer, the signal layer including first and second signal traces connected to the first and second signal vias, respectively, the signal layer further including a ground conductor located between the signal traces and adjacent signal-carrying elements.

公开(公告)号：US11726373B2

公开(公告)日：2023-08-15

申请号：US17972144

申请日：2022-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Shunpei Yamazaki

IPC: G02F1/1345 ,  G09G3/20 ,  H05K1/11 ,  H05K3/36 ,  G02F1/133 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1339 ,  G02F1/1341 ,  G02F1/1368 ,  H01L27/12 ,  H05K1/14 ,  H05K1/02 ,  G09G3/36

CPC classification number: G02F1/13452 ,  G02F1/1339 ,  G02F1/1341 ,  G02F1/1368 ,  G02F1/13306 ,  G02F1/13394 ,  G02F1/133345 ,  G02F1/133512 ,  G02F1/133514 ,  G09G3/20 ,  G09G3/2092 ,  H01L27/1222 ,  H05K1/117 ,  H05K1/148 ,  H05K3/361 ,  G09G3/3614 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2300/08 ,  G09G2310/0264 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2330/08 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/0265 ,  H05K2201/094 ,  H05K2201/09727 ,  H05K2201/10136 ,  H05K2201/10166 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

公开(公告)号：US20190124767A1

公开(公告)日：2019-04-25

申请号：US16169340

申请日：2018-10-24

Applicant: IBIDEN CO., LTD.

Inventor： Takema ADACHI ,  Toshihide MAKINO ,  Hidetoshi NOGUCHI

IPC: H05K1/11 ,  H05K3/46 ,  H05K1/03 ,  H05K3/06 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K1/0373 ,  H05K3/06 ,  H05K3/422 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/09227 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09727 ,  H05K2201/09827 ,  H05K2201/099 ,  H05K2203/072 ,  H05K2203/107 ,  H05K2203/1572

Abstract: A printed wiring board includes: a core substrate having a core layer, first and second conductor layers, and through-hole conductors penetrating through the core layer and connecting the conductor layers; and first and second build-up layers each including an insulating layer, an inner side conductor layer, an outermost insulating layer, an outermost conductor layer, and a solder resist layer. Each of the conductor layers includes conductor circuits having substantially a trapezoid cross-sectional shape, and spaces between adjacent conductor circuits, and includes a metal foil, a seed layer, and an electrolytic plating film. The inner side conductor layers have the smallest minimum circuit width, the smallest minimum space width and the largest base angle among the conductor layers. The insulating layers have the smallest ten-point average roughness rz3, rz7 among the ten-point average roughness rz3, rz7, rz1, rz2, rz5 and rz9 of the core layer, insulating layers and outermost insulating layers.

公开(公告)号：US20180213636A1

公开(公告)日：2018-07-26

申请号：US15928090

申请日：2018-03-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： JINWOO CHOI ,  SUNGJUN CHUN ,  JASON L. FRANKEL ,  PAUL R. WALLING ,  ROGER D. WEEKLY

IPC: H05K1/02 ,  G06F17/50

CPC classification number: H05K1/0224 ,  G06F17/5081 ,  H05K1/116 ,  H05K2201/09681 ,  H05K2201/09718 ,  H05K2201/09727 ,  Y10T29/49004 ,  Y10T29/49155 ,  Y10T29/53022

Abstract: A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.

公开(公告)号：US20180160543A1

公开(公告)日：2018-06-07

申请号：US15430556

申请日：2017-02-13

Applicant: Unimicron Technology Corp.

Inventor： Po-Hsuan Liao ,  Chi-Min Chang ,  Cheng-Po Yu

IPC: H05K3/20 ,  H05K3/38 ,  H05K1/11

CPC classification number: H05K3/20 ,  H05K3/4644 ,  H05K2201/09727 ,  H05K2201/09918 ,  H05K2203/0522 ,  H05K2203/107 ,  H05K2203/1476

Abstract: A manufacturing method of a circuit board including the following steps is provided. A first patterned circuit layer is formed on a surface of a circuit substrate, and the first patterned circuit layer exposes a portion of the surface of the circuit substrate. A patterned glue layer is formed on the portion of the surface of the circuit substrate exposed by the first patterned circuit layer. A second patterned circuit layer is transfer-printed on the corresponding patterned glue layer. In addition, a structure of the circuit board is also mentioned.

公开(公告)号：US09977558B2

公开(公告)日：2018-05-22

申请号：US15483247

申请日：2017-04-10

Applicant: Japan Display Inc.

Inventor： Hayato Kurasawa ,  Keisuke Asada ,  Tatsuya Ide ,  Koji Ishizaki

IPC: G06F3/044 ,  G06F3/041 ,  H05K1/02 ,  H05K1/14

CPC classification number: G06F3/044 ,  G02F1/13338 ,  G06F3/0412 ,  G06F2203/04108 ,  G06F2203/04112 ,  H05K1/028 ,  H05K1/117 ,  H05K1/147 ,  H05K3/28 ,  H05K3/361 ,  H05K2201/09263 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/10128

Abstract: According to one embodiment, a detection device includes a substrate, detection electrode, terminal formed of a metal material, lead, coating layer, conductive adhesion layer, and circuit board. The lead connects the electrode and the terminal. The coating layer covers the electrode and the lead, and partly covers the terminal. The adhesion layer covers a part of the terminal exposed from the coating layer and covers a part of the coating layer. The circuit board is connected to the terminal with the adhesion layer interposed therebetween. At least in an overlapping area where the adhesion layer covers the coating layer, an area of the metal material per unit area is smaller than that of the other area of the terminal.

公开(公告)号：US09955567B2

公开(公告)日：2018-04-24

申请号：US14341834

申请日：2014-07-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jinwoo Choi ,  Sungjun Chun ,  Jason L. Frankel ,  Paul R. Walling ,  Roger D. Weekly

IPC: H05K1/02 ,  G06F17/50 ,  H05K1/11

CPC classification number: H05K1/0224 ,  G06F17/5081 ,  H05K1/116 ,  H05K2201/09681 ,  H05K2201/09718 ,  H05K2201/09727 ,  Y10T29/49004 ,  Y10T29/49155 ,  Y10T29/53022

Abstract: A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.

公开(公告)号：US09905973B2

公开(公告)日：2018-02-27

申请号：US14949958

申请日：2015-11-24

Applicant: CommScope, Inc. of North Carolina

Inventor： Richard A. Schumacher

IPC: H01R13/6473 ,  H01R13/6461 ,  H01R24/62 ,  H01R13/6466 ,  H05K1/16 ,  H01R24/64 ,  H05K1/02 ,  H05K1/11

CPC classification number: H01R13/6473 ,  H01R13/6466 ,  H01R24/64 ,  H05K1/0219 ,  H05K1/0228 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/117 ,  H05K1/165 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/1034 ,  H05K2201/10356

Abstract: Communications plugs are provided that include a housing that receives the conductors of the communication cable. A printed circuit board is mounted at least partially within the housing. A plurality of plug contacts are on the printed circuit board, and the printed circuit board includes a plurality of conductive paths that electrically connect respective ones of the conductors to respective ones of the plug contacts. First and second of the conductive paths are arranged as a first differential pair of conductive paths that comprise a portion of a first differential transmission line through the communications plug, where the first differential transmission line includes a first transition region where the impedance of the first differential transmission line changes by at least 20% and a second transition region impedance of the first differential transmission line changes by at least 20%.

公开(公告)号：US20180035533A1

公开(公告)日：2018-02-01

申请号：US15659187

申请日：2017-07-25

Applicant: QUALCOMM Incorporated

Inventor： Priyatharshan Pathmanathan

IPC: H05K1/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H05K1/0236 ,  G06F13/4086 ,  H01L23/5227 ,  H01L23/5286 ,  H05K1/0213 ,  H05K1/0225 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/029 ,  H05K2201/09727 ,  H05K2201/10159

Abstract: A system includes: a printed circuit board having a plurality of conductive traces; a processing device coupled to the printed circuit board and in electrical communication with the plurality of conductive traces; a first memory module and a second memory module in electrical communication with the plurality of conductive traces and sharing channels of the conductive traces, wherein the first memory module is physically more proximate to the processing device than is the second memory module; and an electronic band gap (EBG) structure physically disposed in an area between the first memory module and the second memory module.