公开(公告)号：US5127749A

公开(公告)日：1992-07-07

申请号：US719024

申请日：1991-06-21

Applicant: John A. Tiano, Jr. ,  Michel Vallet ,  Joseph L. Costa

Inventor： John A. Tiano, Jr. ,  Michel Vallet ,  Joseph L. Costa

IPC: B41J2/265

CPC classification number: B41J2/265 ,  Y10T29/49726 ,  Y10T29/49746

Abstract: A method of repairing a spent printhead or printhead subassembly and a repaired printhead or printhead subassembly made in accordance with such method is disclosed. The method includes the steps of removing the print pins from the spent printhead or printhead subassembly, removing at least a portion of the nose section in the area of the print pin holes of the spent printhead or printhead subassembly, filling at least a portion of such removed portion of the nose section with a casting material, inserting guide wires into the print pin holes in the nose section and permitting the casting material to at least partially cure to form new print pin holes. Also disclosed is a printhead or printhead subassembly repaired from a spent printhead having original print pin holes, the repaired printhead having a first section which includes a plurality of original print pin holes and a second section which includes a plurality of repaired print pin holes, the original print pin holes and repaired print pin holes being in alignment so as to form a plurality of composite print pin holes in the nose section, and a plurality of print pins arranged in the plurality of composite print pin holes so as to be selectively extendable beyond the print surface with the guidance of the repaired print pin holes of the second section.

Abstract translation: 公开了一种修复耗尽的打印头或打印头子组件以及根据这种方法制造的修理的打印头或打印头子组件的方法。 该方法包括以下步骤：从已用完的打印头或打印头子组件上移除打印销，在废打印头或打印头子组件的打印针孔的区域中移除鼻部部分的至少一部分，填充其中至少一部分 通过铸造材料去除鼻部的部分，将引导线插入鼻部中的打印针孔中，并允许铸造材料至少部分固化以形成新的打印针孔。 还公开了一种从具有原始打印针孔的废打印头修复的打印头或打印头子组件，修理的打印头具有包括多个原始打印针孔的第一部分和包括多个修复的打印针孔的第二部分， 原始打印针孔和修复的打印针孔对准，以便在鼻部中形成多个复合打印针孔，以及多个打印销，布置在多个复合打印针孔中，以便可选择地延伸超出 在第二部分的修理的打印针孔的引导下打印表面。

公开(公告)号：US20050029661A1

公开(公告)日：2005-02-10

申请号：US10839761

申请日：2004-05-05

Applicant: Michel Vallet ,  Sylvain Kritter

Inventor： Michel Vallet ,  Sylvain Kritter

IPC: G01R31/307 ,  H01L23/58 ,  H01L29/40 ,  G01R31/26

CPC classification number: G01R31/307 ,  H01L22/32

Abstract: An integrated circuit is provided that includes an active region and at least one interconnect part. The interconnect part is located above the active region, and includes a plurality of metallization levels and at least one test pad. The test pad is located in one of the metallization levels that is beneath a top one of the metallization levels. In a preferred embodiment, the test pad is located beneath supply lines. Also provided is a method for testing such an integrated circuit.

Abstract translation: 提供了一种集成电路，其包括有源区和至少一个互连部。 互连部分位于有源区上方，并且包括多个金属化层和至少一个测试焊盘。 测试垫位于金属化水平的顶部之下的金属化水平之一。 在优选实施例中，测试垫位于供应线下方。 还提供了一种用于测试这种集成电路的方法。

公开(公告)号：US06175240B1

公开(公告)日：2001-01-16

申请号：US09169356

申请日：1998-10-09

Applicant: Michel Vallet

Inventor： Michel Vallet

IPC: G01R3100

CPC classification number: G01R31/307

Abstract: DC voltage levels applied to an integrated circuit are measured using an electron beam. A pulsed signal having a peak voltage dependent upon or representing one of the DC voltage level applied to the integrated circuit is first generated. The pulsed signal is applied to a test zone, and the voltage of the test zone varies according to the pulsed signal. The DC voltage level applied to the test zone on the integrated circuit transforms into a pulsed voltage. An electron beam is then used to measure the voltage of the test zone.

Abstract translation: 使用电子束测量施加到集成电路的直流电压电平。 首先产生具有取决于或表示施加到集成电路的DC电压电平之一的峰值电压的脉冲信号。 脉冲信号被施加到测试区域，并且测试区域的电压根据脉冲信号而变化。 施加到集成电路上的测试区域的直流电压电平转换成脉冲电压。 然后使用电子束来测量测试区域的电压。

公开(公告)号：US07196421B2

公开(公告)日：2007-03-27

申请号：US10839770

申请日：2004-05-05

Applicant: Michel Vallet

Inventor： Michel Vallet

IPC: H01L23/48

CPC classification number: H01L23/544 ,  H01L23/528 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is provided that includes at least one metallization level having a plurality of dummy conductors. At least one of the dummy conductors has an oriented shape made up of a plurality of non-parallel rectangles in mutual contact. In one embodiment, the at least one dummy conductor is in the form of an “L”. In another embodiment, the at least one dummy conductor is in the form of a Latin cross. In yet another embodiment, the at least one dummy conductor is in the form of a “T”.

Abstract translation: 提供一种集成电路，其包括具有多个虚拟导体的至少一个金属化层。 虚拟导体中的至少一个具有由相互接触的多个非平行矩形构成的定向形状。 在一个实施例中，至少一个虚拟导体是“L”的形式。 在另一个实施例中，至少一个虚拟导体是拉丁十字的形式。 在另一个实施例中，至少一个虚拟导体是“T”的形式。

公开(公告)号：US06539276B1

公开(公告)日：2003-03-25

申请号：US09407507

申请日：1999-09-28

Applicant: Michel Vallet

Inventor： Michel Vallet

IPC: G06F1900

CPC classification number: G03F7/70483 ,  G03F9/00 ,  H01L21/68 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor circuit that includes components and registration features that are electrically isolated from the components. The registration features form projecting parts that are uniformly distributed in the form of a matrix over at least part of the external surface of the circuit so as to define adjacent registration areas. In a preferred embodiment, the semiconductor circuit also includes metal registration features that are produced in at least one metallization level of the circuit. Also provided is a method of adjusting a tool so as to put it into a particular position with respect to the surface of a semiconductor circuit that has registration features defining adjacent registration areas. According to the method, an at least partial topographic record of the registration features on the surface of the semiconductor circuit is produced, and the registration features of the topographic record are brought into coincidence with reference features of a reference drawing. The reference features of the reference drawing correspond to the registration features of the circuit. The position of the tool is adjusted with respect to at least some of the reference features or registration features.

Abstract translation: 一种半导体电路，包括与部件电隔离的部件和对准特征。 配准特征形成在电路的外表面的至少一部分上以矩阵的形式均匀分布的突出部分，以便限定相邻的配准区域。 在优选实施例中，半导体电路还包括在电路的至少一个金属化级别中产生的金属配准特征。 还提供了一种调整工具以使其相对于具有限定相邻配准区域的配准特征的半导体电路的表面的特定位置的方法。 根据该方法，产生半导体电路表面上的配准特征的至少部分地形记录，并且使地形记录的配准特征与参考图的参考特征一致。 参考图的参考特征对应于电路的配准特征。 工具的位置相对于至少一些参考特征或登记特征进行调整。

公开(公告)号：US06211688B1

公开(公告)日：2001-04-03

申请号：US09166017

申请日：1998-10-05

Applicant: Michel Vallet

Inventor： Michel Vallet

IPC: G01R104

CPC classification number: G01R31/2884

Abstract: The invention relates to a test area of an electronic circuit comprising a contact point formed in the surface of a substrate. The test area also includes spaced apart radially extending bosses adjacent the contact point for guiding a test probe positioned on the surface of the substrate to the contact point.

Abstract translation: 本发明涉及一种电子电路的测试区域，该测试区域包括形成在基板表面上的接触点。 测试区域还包括与接触点相邻的间隔开的径向延伸的凸台，用于将位于衬底表面上的测试探针引导到接触点。

公开(公告)号：US20060157699A1

公开(公告)日：2006-07-20

申请号：US11302409

申请日：2005-12-12

Applicant: Michel Vallet ,  Philippe Sardin ,  Thierry Parrassin ,  Sylvain Dudit

Inventor： Michel Vallet ,  Philippe Sardin ,  Thierry Parrassin ,  Sylvain Dudit

IPC: H01L23/58

CPC classification number: G01R31/311 ,  G02B6/00 ,  G02B6/42 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test structure for integrated electronic circuits having a substantially planar substrate coated with a plurality of metallization layers comprises a switching element formed on the surface of the substrate. It also comprises a tunnel formed in one or more metallization layers between the top of the switching element and the front side of the integrated circuit. This tunnel is designed to channel photons emitted by the switching element towards the front side.

Abstract translation: 具有涂覆有多个金属化层的基本平坦的基板的集成电子电路的测试结构包括形成在基板的表面上的开关元件。 它还包括在开关元件的顶部和集成电路的前侧之间的一个或多个金属化层中形成的隧道。 该隧道被设计成将由开关元件发射的光子向前侧传播。

公开(公告)号：US20050006772A1

公开(公告)日：2005-01-13

申请号：US10839770

申请日：2004-05-05

Applicant: Michel Vallet

Inventor： Michel Vallet

IPC: H01L23/528 ,  H01L23/544 ,  H01L23/52

CPC classification number: H01L23/544 ,  H01L23/528 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is provided that includes at least one metallization level having a plurality of dummy conductors. At least one of the dummy conductors has an oriented shape made up of a plurality of non-parallel rectangles in mutual contact. In one embodiment, the at least one dummy conductor is in the form of an “L”. In another embodiment, the at least one dummy conductor is in the form of a Latin cross. In yet another embodiment, the at least one dummy conductor is in the form of a “T”.

Abstract translation: 提供一种集成电路，其包括具有多个虚拟导体的至少一个金属化层。 虚拟导体中的至少一个具有由相互接触的多个非平行矩形构成的定向形状。 在一个实施例中，至少一个虚拟导体是“L”的形式。 在另一个实施例中，至少一个虚拟导体是拉丁十字的形式。 在另一个实施例中，至少一个虚拟导体是“T”的形式。

公开(公告)号：US06246072B1

公开(公告)日：2001-06-12

申请号：US09193443

申请日：1998-11-17

Applicant: Michel Vallet

Inventor： Michel Vallet

IPC: H01L2976

CPC classification number: G01R31/307 ,  Y10S257/903

Abstract: The present invention relates to an integrated circuit test pad implemented in a surface metallization layer covered with an insulating coating. The pad is surrounded with a first metal ring made in the surface metallization layer and with a second metal ring made in a lower metallization surface, the first and second rings being electrically interconnected by at least one via and set to a fixed potential.

Abstract translation: 本发明涉及一种在覆盖有绝缘涂层的表面金属化层中实现的集成电路测试垫。 衬垫由在表面金属化层中制成的第一金属环和由下金属化表面制成的第二金属环包围，第一和第二环通过至少一个通孔电连接并设定为固定电位。