Semiconductor devices having electrostatic discharge layouts for reduced capacitance

    公开(公告)号:US11158570B2

    公开(公告)日:2021-10-26

    申请号:US15976674

    申请日:2018-05-10

    Abstract: Semiconductor devices having busing layouts configured to reduce on-die capacitance are disclosed herein. In one embodiment, a semiconductor device includes an electrostatic discharge device electrically connected in parallel with an integrated circuit and configured to divert high voltages generated during an electrostatic discharge event away from the integrated circuit. The semiconductor device further includes a signal bus and a power bus electrically connected to the electrostatic discharge device. The signal bus includes a plurality of first fingers grouped into first groups and the power bus includes a plurality of second fingers grouped into second groups. The first groups are positioned generally parallel to and interleaved between the second groups.

    APPARATUS WITH VOLTAGE PROTECTION MECHANISM

    公开(公告)号:US20220359495A1

    公开(公告)日:2022-11-10

    申请号:US17871681

    申请日:2022-07-22

    Abstract: An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

    APPARATUS WITH VOLTAGE PROTECTION MECHANISM

    公开(公告)号:US20210183851A1

    公开(公告)日:2021-06-17

    申请号:US16712851

    申请日:2019-12-12

    Abstract: An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

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