公开(公告)号：US20230236949A1

公开(公告)日：2023-07-27

申请号：US17902714

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Federica CRESCI ,  Nicola DEL GATTO ,  Emanuele CONFANOLIERI

IPC: G06F11/34 ,  G06F12/0893

CPC classification number: G06F11/349 ,  G06F12/0893 ,  G06F2212/601

Abstract: Provided is a system and method for storing, via a processor, in a memory of an application specific integrated circuit (ASIC), one or more threshold values responsive to at least one of physical layer and processing layer operating conditions of the ASIC. Also included is monitoring at least one of a physical layer operating condition value and a processing layer performance condition value of the ASIC, the moderating forming a monitored value, comparing the monitored value with the stored threshold values, and throttling processing layer performance of the ASIC when the monitored value exceeds at least one of the stored threshold values.

公开(公告)号：US20230236729A1

公开(公告)日：2023-07-27

申请号：US17902716

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Federica CRESCI ,  Nicola DEL GATTO ,  Emanuele CONFANOLIERI

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0653 ,  G06F3/0673

Abstract: Provided is a method for regulating, via a hardware performance throttling block (PTB) of a memory module, the performance of a memory system in response to read and write requests from a processing system which hosts the memory system. The host system sends memory service requests to the memory system in the form of memory read requests and memory write requests. The host system may also send requests to throttle, that is, to limit the responses of the memory system in response to memory requests; the host system may also send to the memory system various parameters indicative of current memory usage. In response to the throttling request, the PTB of the memory module either stops any reception of memory requests, or limits (throttles) the number of memory requests (either read requests, write requests, or both) for a specified number of clock/command cycles. The PTB also determines when full, un-throttled performance may be resumed.

公开(公告)号：US20230394140A1

公开(公告)日：2023-12-07

申请号：US17811770

申请日：2022-07-11

Applicant: Micron Technology, Inc.

Inventor： Alessandro ORLANDO ,  Niccolò IZZO ,  Federica CRESCI ,  Angelo Alberto ROVELLI ,  Craig A. JONES ,  Danilo CARACCIO ,  Luca CASTELLAZZI

IPC: G06F21/55

CPC classification number: G06F21/554 ,  G06F2221/034

Abstract: In some implementations, a system includes a set of servers configured to establish a set of virtual machines to provide a computing environment; a set of compute express link (CXL) interface components configured to communicate with the set of servers via a set of CXL interconnects; and a controller configured to at least one of: encrypt protocol data against a CXL interposer security threat associated with the set of CXL interconnects or a malicious extension security threat, provide a secure handshake verification of an identity of the set of CXL interface components, enforce a chain of trust rooted in hardware of the set of CXL interface components; restrict access to an area of memory of the set of CXL interface components that stores security data for verified or secured processes; or perform a security check and set up a set of security features of the set of CXL interface components.