公开(公告)号：US20230396449A1

公开(公告)日：2023-12-07

申请号：US17810952

申请日：2022-07-06

Applicant: Micron Technology, Inc.

Inventor： Alessandro ORLANDO ,  Niccolò IZZO ,  Danilo CARACCIO

IPC: H04L9/32 ,  H04L9/08

CPC classification number: H04L9/3265 ,  H04L9/0825

Abstract: Implementations described herein relate to a device identifier composition engine (DICE) 3-layer architecture. In some implementations, a device may include a secure computing environment including a hardware root of trust (HRoT) DICE component. The secure computing environment may include a DICE layer 0 component configured to derive a DICE identity key. The secure computing environment may include a DICE layer 1 component configured to derive a DICE alias key based on the DICE identity key. The secure computing environment may include a controller configured to receive an update to firmware of a component. The controller may be configured to update the firmware of the component based on receiving the update. The controller may be configured to update one or more keys of the component or one or more keys of one or more components above the component in a layer stack.

公开(公告)号：US20250094278A1

公开(公告)日：2025-03-20

申请号：US18778665

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  Emanuele CONFALONIERI ,  Daniele BALLUCHI ,  Danilo CARACCIO ,  Nicola DEL GATTO ,  Rishabh DUBEY

IPC: G06F11/10

Abstract: Provided in a central controller system, is a system and method to identify and mitigate errors on a die containing mission critical logical-to-physical addressing information. The logical-to-physical (L2P) addressing information is essential for translating logical memory addresses for uncompressed data to physical addresses for compressed data. When a die containing L2P data is detected as being corrupted, the corrupted data is corrected, and all the data is moved to an uncorrupted die at a specified offset from the original address of the die.

公开(公告)号：US20240184929A1

公开(公告)日：2024-06-06

申请号：US18489625

申请日：2023-10-18

Applicant: Micron Technology, Inc.

Inventor： Alessandro ORLANDO ,  Danilo CARACCIO ,  Niccolò IZZO

IPC: G06F21/73 ,  G06F21/60 ,  G06F21/64

CPC classification number: G06F21/73 ,  G06F21/602 ,  G06F21/64

Abstract: Implementations described herein relate to an immutable certificate for a device identifier composition engine (DICE). In some implementations, a device may include a secure computing environment. The secure component environment may include a hardware root of trust (HRoT) DICE component, a DICE layer 0 (L0) component configured to derive a DICE identity key, wherein the DICE L0 component is above the HRoT DICE component in a layer stack, a DICE layer 1 (L1) component configured to derive a DICE alias key based on the DICE identity key, wherein the DICE L1 component is above the DICE L0 component in the layer stack, wherein the DICE L1 component and the DICE L0 component are implemented as mutable code, and a controller. The controller may be configured to generate a set of certificates based on a compound device identifier (CDI).

公开(公告)号：US20240169063A1

公开(公告)日：2024-05-23

申请号：US18511425

申请日：2023-11-16

Applicant: Micron Technology, Inc.

Inventor： Niccolò IZZO ,  Danilo CARACCIO ,  Luca CASTELLAZZI

IPC: G06F21/56

CPC classification number: G06F21/566 ,  G06F2221/034

Abstract: Implementations described herein relate to preventing profiled side channel attacks. A host device may obtain a first profiling configuration that is based on a plurality of keys and one or more characteristics of a first memory device and may obtain a second profiling configuration that is based on the plurality of keys and one or more characteristics of a second memory device. The host device may generate a model based on the first profiling configuration and the second profiling configuration. The host device may initiate or perform a profiled side channel attach using the model.

公开(公告)号：US20230394140A1

公开(公告)日：2023-12-07

申请号：US17811770

申请日：2022-07-11

Applicant: Micron Technology, Inc.

Inventor： Alessandro ORLANDO ,  Niccolò IZZO ,  Federica CRESCI ,  Angelo Alberto ROVELLI ,  Craig A. JONES ,  Danilo CARACCIO ,  Luca CASTELLAZZI

IPC: G06F21/55

CPC classification number: G06F21/554 ,  G06F2221/034

Abstract: In some implementations, a system includes a set of servers configured to establish a set of virtual machines to provide a computing environment; a set of compute express link (CXL) interface components configured to communicate with the set of servers via a set of CXL interconnects; and a controller configured to at least one of: encrypt protocol data against a CXL interposer security threat associated with the set of CXL interconnects or a malicious extension security threat, provide a secure handshake verification of an identity of the set of CXL interface components, enforce a chain of trust rooted in hardware of the set of CXL interface components; restrict access to an area of memory of the set of CXL interface components that stores security data for verified or secured processes; or perform a security check and set up a set of security features of the set of CXL interface components.

公开(公告)号：US20230282258A1

公开(公告)日：2023-09-07

申请号：US18160292

申请日：2023-01-26

Applicant: Micron Technology, Inc.

Inventor： Edmund GIESKE ,  Amitava MAJUMDAR ,  Cagdas DIRIK ,  Sujeet AYYAPUREDDI ,  Yang LU ,  Ameen D. AKEL ,  Danilo CARACCIO ,  Niccolo' IZZO ,  Elliott C. COOPER-BALIS ,  Markus H. GEIGER

IPC: G11C7/24 ,  G11C7/22 ,  G11C29/52

CPC classification number: G11C7/24 ,  G11C7/222 ,  G11C29/52

Abstract: Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

公开(公告)号：US20230238046A1

公开(公告)日：2023-07-27

申请号：US17941655

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Edmund GIESKE ,  Cagdas DIRIK ,  Robert M. WALKER ,  Sujeet AYYAPUREDDI ,  Niccolo IZZO ,  Markus GEIGER ,  Yang LU ,  Ameen AKEL ,  Elliott C. COOPER-BALIS ,  Danilo CARACCIO

IPC: G11C11/406 ,  G11C29/52

CPC classification number: G11C11/40618 ,  G11C11/40611 ,  G11C29/52

Abstract: An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.

公开(公告)号：US20230236735A1

公开(公告)日：2023-07-27

申请号：US17897813

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Sujeet AYYAPUREDDI ,  Yang LU ,  Edmund GIESKE ,  Cagdas DIRIK ,  Ameen D. AKEL ,  Elliott C. COOPER-BALIS ,  Amitava MAJUMDAR ,  Danilo CARACCIO ,  Robert M. WALKER

IPC: G06F3/06 ,  G06F11/07

CPC classification number: G06F3/0616 ,  G06F3/0673 ,  G06F3/0629 ,  G06F11/076 ,  G06F11/073

Abstract: Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).