公开(公告)号：US12124367B2

公开(公告)日：2024-10-22

申请号：US17262476

申请日：2020-12-07

Applicant: Micron Technology, Inc.

Inventor： Junjun Wang ,  Yi Heng Sun

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0253 ,  G06F12/0238 ,  G06F12/0653

Abstract: Methods, systems, and devices for techniques for accessing managed not-AND (NAND) memory are described. An indicator of a first type that indicates whether each physical address in a group of physical addresses stores valid data may be accessed. Indicators of a second type may be used to indicate whether respective physical addresses of the group of physical addresses store valid data. Data stored at the group of physical addresses may be transferred to a different group of physical addresses based on the indicator of the first type. Also, another indicator of the first type that indicates whether each physical address in the different group of physical addresses stores valid data may be updated.

公开(公告)号：US12013789B2

公开(公告)日：2024-06-18

申请号：US17645686

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Yanming Liu ,  Zhenzhen Yang ,  Yi Heng Sun ,  Junjun Wang

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/7201

Abstract: Methods, systems, and devices for flexible information compression at a memory system are described. For example, a memory system may compress information in a change log to reduce the frequency of transfers of one or more mappings between volatile memory and non-volatile memory. The memory system may compress information associated with a sequence of sequentially-indexed addresses by storing the information associated with those addresses at a pair of entries in the change log. The memory system may additionally switch between a first operating mode associated with identifying sequentially-indexed addresses and generating compressed entries, and a second operating mode associated with generating entries of the change log for each address received in commands.

公开(公告)号：US20240411483A1

公开(公告)日：2024-12-12

申请号：US18749469

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Huachen Li ,  Xu Zhang ,  Xing Wang ,  Guan Zhong Wang ,  Tian Liang ,  Junjun Wang

IPC: G06F3/06

Abstract: Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.

公开(公告)号：US20220397953A1

公开(公告)日：2022-12-15

申请号：US17736886

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Junjun Wang ,  Yanming Liu ,  Deping He ,  Hua Tan

IPC: G06F1/3225 ,  G06F1/3296 ,  G06F3/06

Abstract: Methods, systems, and devices for dynamic power control are described. In some examples, a memory device may be configured to adjust a first duration for transitioning power modes. For example, the memory device may be configured to operate in a first power mode, a second power mode, and a third power mode. When operating in a second power mode, the memory device may be configured to increase or decrease the first duration for transitioning to a third power mode based on a second duration between received commands. If no commands are received during the first duration, the memory device may transition from the second power mode to the third power mode.

公开(公告)号：US20250080273A1

公开(公告)日：2025-03-06

申请号：US18830459

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Zhanqiang Su ,  Junjun Wang

IPC: H04L1/00 ,  H04L1/1812 ,  H04L1/20

Abstract: Methods, systems, and devices for enhanced negative acknowledgment control (NAC) frame are described. A device may generate and communicate an enhanced NAC frame that includes additional error information to indicate to the device a cause for the error. The device may receive a data frame and determine an error condition associated with a set of layers of a protocol stack. The device may generate feedback indicating a cause for the determined error condition and transmit the feedback indicating the error cause. The feedback may be a NAC that includes a first quantity of bits configured for indicating an existence of an error and a second quantity of bits configured for indicating the error cause. A format of the NAC frame may include bits configured to identify multiple types of error causes associated with the different layers of the protocol stack.

公开(公告)号：US20240394197A1

公开(公告)日：2024-11-28

申请号：US18668019

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Yanming Liu ,  Zhenzhen Yang ,  Yi Heng Sun ,  Junjun Wang

IPC: G06F12/1009

Abstract: Methods, systems, and devices for flexible information compression at a memory system are described. For example, a memory system may compress information in a change log to reduce the frequency of transfers of one or more mappings between volatile memory and non-volatile memory. The memory system may compress information associated with a sequence of sequentially-indexed addresses by storing the information associated with those addresses at a pair of entries in the change log. The memory system may additionally switch between a first operating mode associated with identifying sequentially-indexed addresses and generating compressed entries, and a second operating mode associated with generating entries of the change log for each address received in commands.

公开(公告)号：US20240187003A1

公开(公告)日：2024-06-06

申请号：US18284805

申请日：2021-05-06

Applicant: Micron Technology, Inc.

Inventor： Junjun Wang

IPC: H03L7/089 ,  H03L7/099 ,  H03L7/183

CPC classification number: H03L7/089 ,  H03L7/0991 ,  H03L7/183

Abstract: A variety of applications can include a phase frequency detector structured to track the falling edges of two input signals to detect a phase difference between the two signals and to generate one or more signals that can be used to adjust one of the signals with respect to the other when the phase difference is greater than 180 degrees. The phase frequency detector can be implemented in a phase lock loop circuit to track the falling edges of a reference clock signal and the falling edge of a feedback signal. In response to detection of the phase difference between the reference clock signal and the feedback signal being greater than 180 degrees using the falling edges of these signals, the phase frequency detector can adjust its output signals to provide for recovery of a lock condition for the reference clock signal. Additional devices, systems, and methods are discussed.

公开(公告)号：US20250094341A1

公开(公告)日：2025-03-20

申请号：US18896407

申请日：2024-09-25

Applicant: Micron Technology, Inc.

Inventor： Junjun Wang ,  Yi Heng Sun

IPC: G06F12/02 ,  G06F12/06

Abstract: Methods, systems, and devices for techniques for accessing managed not-AND (NAND) memory are described. An indicator of a first type that indicates whether each physical address in a group of physical addresses stores valid data may be accessed. Indicators of a second type may be used to indicate whether respective physical addresses of the group of physical addresses store valid data. Data stored at the group of physical addresses may be transferred to a different group of physical addresses based on the indicator of the first type. Also, another indicator of the first type that indicates whether each physical address in the different group of physical addresses stores valid data may be updated.

公开(公告)号：US12039194B2

公开(公告)日：2024-07-16

申请号：US17050334

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Huachen Li ,  Xu Zhang ,  Xing Wang ,  Guan Zhong Wang ,  Tian Liang ,  Junjun Wang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/0688

Abstract: Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.

公开(公告)号：US20240039656A1

公开(公告)日：2024-02-01

申请号：US17815912

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Zhanqiang Su ,  Junjun Wang

IPC: H04L1/00 ,  H04L1/20 ,  H04L1/18

CPC classification number: H04L1/0061 ,  H04L1/203 ,  H04L1/1819

Abstract: Methods, systems, and devices for enhanced negative acknowledgment control (NAC) frame are described. A device may generate and communicate an enhanced NAC frame that includes additional error information to indicate to the device a cause for the error. The device may receive a data frame and determine an error condition associated with a set of layers of a protocol stack. The device may generate feedback indicating a cause for the determined error condition and transmit the feedback indicating the error cause. The feedback may be a NAC that includes a first quantity of bits configured for indicating an existence of an error and a second quantity of bits configured for indicating the error cause. A format of the NAC frame may include bits configured to identify multiple types of error causes associated with the different layers of the protocol stack.