公开(公告)号：US12216905B2

公开(公告)日：2025-02-04

申请号：US17632099

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Xing Wang ,  Wenyu Li ,  Xiaolai Zhu ,  Xu Zhang

IPC: G06F3/06

Abstract: Techniques are described herein for performing a flush operation for a write booster buffer of a memory system. The flush operation may include swapping valid blocks in the write booster buffer for invalid blocks in a storage space of the memory system. After swapping the blocks, the memory system may transfer the information from a first type of blocks that were formerly assigned to the write booster buffer to a second type of blocks in the storage space. In such a flush operation, space is made available in the write booster buffer with less latency than it would take to transfer information between blocks, thereby improving the performance of the write booster mode.

公开(公告)号：US20230342077A1

公开(公告)日：2023-10-26

申请号：US17050334

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Huachen Li ,  Xu Zhang ,  Xing Wang ,  Guan Zhong Wang ,  Tian Liang ,  Junjun Wang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/0688

Abstract: Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.

公开(公告)号：US20250086115A1

公开(公告)日：2025-03-13

申请号：US18886191

申请日：2024-09-16

Applicant: Micron Technology, Inc.

Inventor： Xing Wang ,  Zhen Gu ,  Xu Zhang ,  Liping Xu

IPC: G06F12/0873

Abstract: Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.

公开(公告)号：US20230376206A1

公开(公告)日：2023-11-23

申请号：US17632099

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Xing Wang ,  Wenyu Li ,  Xiaolai Zhu ,  Xu Zhang

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0679

Abstract: Techniques are described herein for performing a flush operation for a write booster buffer of a memory system. The flush operation may include swapping valid blocks in the write booster buffer for invalid blocks in a storage space of the memory system. After swapping the blocks, the memory system may transfer the information from a first type of blocks that were formerly assigned to the write booster buffer to a second type of blocks in the storage space. In such a flush operation, space is made available in the write booster buffer with less latency than it would take to transfer information between blocks, thereby improving the performance of the write booster mode.

公开(公告)号：US20230350579A1

公开(公告)日：2023-11-02

申请号：US17637428

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Xing Wang ,  Liu Yang ,  Xiaolai Zhu ,  Bin Zhao

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.

公开(公告)号：US11409462B2

公开(公告)日：2022-08-09

申请号：US16959064

申请日：2019-12-31

Applicant: Micron Technology, Inc.

Inventor： Huachen Li ,  Xu Zhang ,  Zhong Xian Li ,  Xinghui Duan ,  Xing Wang ,  Tian Liang

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0882

Abstract: Devices and techniques for data removal marking in a memory device are described herein. A delete command can be received at the memory device. A count of data portions in the delete command can be compared to determine whether the count is below a threshold. In response to determining that the count of data portions is below the threshold, the data portions can be written to a buffer. When a buffer full event is detected, a segment of an L2P data structure can be loaded into working memory of the memory device. Then, each record in the segment of the L2P data structure that has a corresponding entry in the buffer can be updated to mark the data as removable (e.g., invalid).

公开(公告)号：US20240394196A1

公开(公告)日：2024-11-28

申请号：US18646589

申请日：2024-04-25

Applicant: Micron Technology, Inc.

Inventor： Xing Wang ,  Liping Xu ,  Xu Zhang ,  Zhen Gu

IPC: G06F12/10

Abstract: Methods, systems, and devices for logical-to-physical (L2P) mapping compression techniques are described. A memory system may use an L2P mapping to map logical addresses to physical addresses of the memory system. The L2P mapping may be a hierarchical L2P mapping divided into multiple levels or subsets that are used to identify a physical address corresponding to a logical address. The memory system may write data to a set of physical addresses that are consecutively indexed and may set a flag in an entry of a second-level of the L2P mapping (e.g., of a three-level L2P mapping) to indicate that the entry is associated with a starting physical address of the consecutively indexed physical addresses. The memory system may subsequently read the data starting at the starting physical address based on the flag (e.g., bypassing reading an entry of a lowest-level of the L2P mapping to determine the physical address).

公开(公告)号：US12111769B2

公开(公告)日：2024-10-08

申请号：US17630453

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Xing Wang ,  Zhen Gu ,  Xu Zhang ,  Liping Xu

IPC: G06F12/0873

CPC classification number: G06F12/0873

Abstract: Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.

公开(公告)号：US12039194B2

公开(公告)日：2024-07-16

申请号：US17050334

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Huachen Li ,  Xu Zhang ,  Xing Wang ,  Guan Zhong Wang ,  Tian Liang ,  Junjun Wang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/0688

Abstract: Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.

公开(公告)号：US11989133B2

公开(公告)日：2024-05-21

申请号：US17637429

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Xing Wang ,  Liping Xu ,  Xu Zhang ,  Zhen Gu

IPC: G06F12/10

CPC classification number: G06F12/10

Abstract: Methods, systems, and devices for logical-to-physical (L2P) mapping compression techniques are described. A memory system may use an L2P mapping to map logical addresses to physical addresses of the memory system. The L2P mapping may be a hierarchical L2P mapping divided into multiple levels or subsets that are used to identify a physical address corresponding to a logical address. The memory system may write data to a set of physical addresses that are consecutively indexed and may set a flag in an entry of a second-level of the L2P mapping (e.g., of a three-level L2P mapping) to indicate that the entry is associated with a starting physical address of the consecutively indexed physical addresses. The memory system may subsequently read the data starting at the starting physical address based on the flag (e.g., bypassing reading an entry of a lowest-level of the L2P mapping to determine the physical address).