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    Command triggered power gating for a memory device
    1.
    发明授权
    Command triggered power gating for a memory device 有权

    公开(公告)号：US11935614B2

    公开(公告)日：2024-03-19

    申请号：US17873911

    申请日：2022-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Hiroshi Akamatsu ,  Kwang-Ho Cho

    IPC: G11C16/04 ,  G06F3/06 ,  G06F11/08 ,  G11C5/14

    CPC classification number: G11C5/148 ,  G06F3/0625 ,  G06F3/0659 ,  G06F11/08

    Abstract: Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.

    TRIPLE ACTIVATE COMMAND ROW ADDRESS LATCHING
    2.
    发明公开
    TRIPLE ACTIVATE COMMAND ROW ADDRESS LATCHING 审中-公开

    公开(公告)号：US20240069759A1

    公开(公告)日：2024-02-29

    申请号：US17899222

    申请日：2022-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Kwang-Ho Cho ,  Miki Matsumoto ,  Kevin J. Ryan

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673

    Abstract: Methods, systems, and devices for triple activate command row address latching are described. For instance, a memory device may receive a first activate command that indicates a first set of bits of a row address, a second activate command that indicates a second set of bits of the row address, and a third activate command that indicates a third set of bits of the row address. The memory device may activate a page of memory based on receiving the first activate command, the second activate command, and the third activate command, where the page of memory is addressed according to the first set of bits, the second set of bits, and the third set of bits.

    ACTIVATE INFORMATION ON PRECEDING COMMAND
    3.
    发明申请
    ACTIVATE INFORMATION ON PRECEDING COMMAND 有权

    公开(公告)号：US20240393979A1

    公开(公告)日：2024-11-28

    申请号：US18792843

    申请日：2024-08-02

    Applicant: Micron Technology, Inc.

    Inventor： John David Porter ,  Bryan David Kerstetter ,  Kwang-Ho Cho

    IPC: G06F3/06

    Abstract: A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.

    Row address latching for multiple activate command protocol
    5.
    发明授权
    Row address latching for multiple activate command protocol 有权

    公开(公告)号：US11972123B2

    公开(公告)日：2024-04-30

    申请号：US17899305

    申请日：2022-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Kwang-Ho Cho ,  Miki Matsumoto

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

    Abstract: Methods, systems, and devices for row address latching for multiple activate command protocol are described. A memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. The memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. The memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.

    HYBRID GAP CONTROLLED MULTI-CLOCK CYCLE MEMORY COMMAND PROTOCOL
    6.
    发明公开
    HYBRID GAP CONTROLLED MULTI-CLOCK CYCLE MEMORY COMMAND PROTOCOL 审中-公开

    公开(公告)号：US20240210986A1

    公开(公告)日：2024-06-27

    申请号：US18528101

    申请日：2023-12-04

    Applicant: Micron Technology, Inc.

    Inventor： Kwang-Ho Cho

    IPC: G06F1/06

    CPC classification number: G06F1/06

    Abstract: Systems and methods for providing memory access commands to memory circuitry using a gap controlled multi-clock cycle memory command protocol is described. More than one memory commands are combined into one multi-clock cycle memory command using gap controlled multi-clock cycle memory command protocol. The number of clock cycles included in the gap between two clock cycles in the multi-clock cycle memory command is controlled and adjustable.

    ROW ADDRESS LATCHING FOR MULTIPLE ACTIVATE COMMAND PROTOCOL
    7.
    发明公开
    ROW ADDRESS LATCHING FOR MULTIPLE ACTIVATE COMMAND PROTOCOL 审中-公开

    公开(公告)号：US20240201878A1

    公开(公告)日：2024-06-20

    申请号：US18593620

    申请日：2024-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Kwang-Ho Cho ,  Miki Matsumoto

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

    Abstract: Methods, systems, and devices for row address latching for multiple activate command protocol are described. A memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. The memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. The memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.

    ROW ADDRESS LATCHING FOR MULTIPLE ACTIVATE COMMAND PROTOCOL
    8.
    发明公开
    ROW ADDRESS LATCHING FOR MULTIPLE ACTIVATE COMMAND PROTOCOL 审中-公开

    公开(公告)号：US20240069760A1

    公开(公告)日：2024-02-29

    申请号：US17899305

    申请日：2022-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Kwang-Ho Cho ,  Miki Matsumoto

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

    Abstract: Methods, systems, and devices for row address latching for multiple activate command protocol are described. A memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. The memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. The memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.

    Multi-clock cycle memory command protocol
    10.
    发明授权
    Multi-clock cycle memory command protocol 有权

    公开(公告)号：US11631442B1

    公开(公告)日：2023-04-18

    申请号：US17556619

    申请日：2021-12-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kwang-Ho Cho

    IPC: G11C7/10 ,  G11C7/22

    Abstract: Systems and methods for providing memory access commands to memory circuitry using a multi-clock cycle memory command protocol is described. A command decoder (or controller) of the memory circuitry may efficiently receive a memory access request (or a memory command) provided using multiple clock cycles. For example, the command decoder may receive a header and a first portion of address bits of target memory cells of the memory command in a first clock cycle and a second portion of the address bits of the target memory cells in a subsequent clock cycle. Accordingly, the memory circuitry may receive a memory command provided over multiple clock cycles with one header. Such memory commands may efficiently include a high number of address bits received using input circuitry of the memory circuitry.

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