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公开(公告)号：US20230359361A1
公开(公告)日：2023-11-09
申请号：US17662187
申请日：2022-05-05
IPC分类号： G06F3/06
CPC分类号： G06F3/0613 , G06F3/0619 , G06F3/0659 , G06F3/0679
摘要： Methods, systems, and devices for frequency regulation for memory management commands are described. A memory device may maintain a respective first counter and second counter for each monitoring area of the memory device, where the counters may be incremented for each activate command received for the corresponding monitoring area. If the first counter satisfies a first threshold, an activate command issued to the monitoring area may be ignored. If the second counter fails to satisfy a second threshold, a memory management command issued to the monitoring area may be ignored and the memory device may maintain a value of the second counter, while decrementing the first counter. Alternatively, if the second counter satisfies the second threshold, the memory device may perform a memory management operation associated with a received memory management command and may decrement the first counter and the second counter.
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公开(公告)号：US12086425B2
公开(公告)日：2024-09-10
申请号：US17730755
申请日：2022-04-27
IPC分类号： G06F3/06
CPC分类号： G06F3/0622 , G06F3/0604 , G06F3/0652 , G06F3/0659 , G06F3/0679
摘要： Methods, systems, and devices for techniques for non-volatile data protection are described. As part of a power on operation, a non-volatile memory system may be configured to selectively stored data. For example, the memory system may determine whether a host system is authorized to access data stored in the memory system prior to a power off operation. If the memory system determines that the host system is authorized, the memory device may retain the data. If the memory system determines that the host system is not authorized, the memory system may erase all or a portion of the data. In some cases, the memory system may maintain a retain flag to determine whether the host system is authorized. Additionally or alternatively, the memory system may determine whether a password received from the host system is valid to determine whether the host system is authorized.
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公开(公告)号：US20230350574A1
公开(公告)日：2023-11-02
申请号：US17731100
申请日：2022-04-27
发明人： Bryan David Kerstetter , Donald M. Morgan , Alan J. Wilson , John David Porter , Jeffrey P. Wright
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F3/0676
摘要： Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.
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公开(公告)号：US12112831B2
公开(公告)日：2024-10-08
申请号：US17877592
申请日：2022-07-29
CPC分类号： G11C7/24 , G11C7/1063 , G11C7/1066 , G11C8/20
摘要： Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.
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公开(公告)号：US12086415B2
公开(公告)日：2024-09-10
申请号：US17662187
申请日：2022-05-05
IPC分类号： G06F3/06
CPC分类号： G06F3/0613 , G06F3/0619 , G06F3/0659 , G06F3/0679
摘要： Methods, systems, and devices for frequency regulation for memory management commands are described. A memory device may maintain a respective first counter and second counter for each monitoring area of the memory device, where the counters may be incremented for each activate command received for the corresponding monitoring area. If the first counter satisfies a first threshold, an activate command issued to the monitoring area may be ignored. If the second counter fails to satisfy a second threshold, a memory management command issued to the monitoring area may be ignored and the memory device may maintain a value of the second counter, while decrementing the first counter. Alternatively, if the second counter satisfies the second threshold, the memory device may perform a memory management operation associated with a received memory management command and may decrement the first counter and the second counter.
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公开(公告)号：US12073120B2
公开(公告)日：2024-08-27
申请号：US17965584
申请日：2022-10-13
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0673
摘要： A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.
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公开(公告)号：US20230350580A1
公开(公告)日：2023-11-02
申请号：US17730755
申请日：2022-04-27
IPC分类号： G06F3/06
CPC分类号： G06F3/0622 , G06F3/0604 , G06F3/0652 , G06F3/0659 , G06F3/0679
摘要： Methods, systems, and devices for techniques for non-volatile data protection are described. As part of a power on operation, a non-volatile memory system may be configured to selectively stored data. For example, the memory system may determine whether a host system is authorized to access data stored in the memory system prior to a power off operation. If the memory system determines that the host system is authorized, the memory device may retain the data. If the memory system determines that the host system is not authorized, the memory system may erase all or a portion of the data. In some cases, the memory system may maintain a retain flag to determine whether the host system is authorized. Additionally or alternatively, the memory system may determine whether a password received from the host system is valid to determine whether the host system is authorized.
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公开(公告)号：US20240231635A1
公开(公告)日：2024-07-11
申请号：US18405998
申请日：2024-01-05
CPC分类号： G06F3/0616 , G06F3/0653 , G06F3/0679 , G06F21/566 , G06F2221/034
摘要： A system for providing maximum row active time enforcement for memory devices is disclosed. A host device issues an activate command to activate a memory bank of a plurality of memory banks of a memory. The memory device activates the memory bank and determines whether a precharge command to close the first memory bank has been issued by the host device within a maximum threshold amount of time since issuance of the activate command. If the system determines that the precharge command has been issued by the host device within the threshold, the memory device closes the memory bank via the host-issued precharge command. If, however, the system determines that the precharge command has not been issued by the host device within the threshold, the memory device internally issues a precharge command to close the memory bank to reduce potential data loss and other harmful effects to the memory device.
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公开(公告)号：US20240126476A1
公开(公告)日：2024-04-18
申请号：US17965584
申请日：2022-10-13
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0673
摘要： A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.
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公开(公告)号：US20240086319A1
公开(公告)日：2024-03-14
申请号：US17941592
申请日：2022-09-09
CPC分类号： G06F12/0292 , G11C29/10 , G06F2212/1032 , G06F2212/657
摘要： A memory device for extending addressable array space by incorporating virtual and physical memory arrays is disclosed. When extra storage space beyond a physical memory array is needed by a controller of the memory device, the storage space may be provided by extending the address space using a virtual array. The memory device incorporates the use of an extra row address bit to increase the addressable space, whereby the extra bit is utilized to address virtual rows in the virtual array. Spare or redundant physical memory elements utilized for memory repair may be programmed to a virtual address space for the virtual memory array. When a memory device operation is activated, the extra row address bit is set to high, and the virtual row address matches with a spare or redundant memory element, the virtual row in the virtual array space is activated for performance of the operation.
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