公开(公告)号：US20240128207A1

公开(公告)日：2024-04-18

申请号：US18542084

申请日：2023-12-15

Applicant: Micron Technology, Inc.

Inventor： Martin Jared Barclay ,  Mark Tunik

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/535 ,  H10B20/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

CPC classification number: H01L23/562 ,  H01L21/7684 ,  H01L21/76895 ,  H01L23/535 ,  H10B20/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

Abstract: Disclosed is a three-dimensional memory device. In one embodiment, a device is disclosed comprising a source plate; plugs fabricated on or partially formed in the source plate; a stack formed on the substrate and plugs comprising alternating insulating layers and conductive layers and channel-material strings of memory cells extending through the insulating layers and conductive layers; a first set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates atop a respective plug in the plurality of plugs; and a second set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate.

公开(公告)号：US11862573B2

公开(公告)日：2024-01-02

申请号：US16984962

申请日：2020-08-04

Applicant: Micron Technology, Inc.

Inventor： Martin Jared Barclay ,  Mark Tunik

IPC: H01L23/00 ,  H01L23/535 ,  H01L21/768 ,  H10B20/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

CPC classification number: H01L23/562 ,  H01L21/7684 ,  H01L21/76895 ,  H01L23/535 ,  H10B20/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

Abstract: Disclosed is a three-dimensional memory device. In one embodiment, a device is disclosed comprising a source plate; plugs fabricated fabricated on or partially formed in the source plate; a stack formed on the substrate and plugs comprising alternating insulating layers and conductive layers and channel-material strings of memory cells extending through the insulating layers and conductive layers; a first set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates atop a respective plug in the plurality of plugs; and a second set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate.