公开(公告)号：US11862573B2

公开(公告)日：2024-01-02

申请号：US16984962

申请日：2020-08-04

Applicant: Micron Technology, Inc.

Inventor： Martin Jared Barclay ,  Mark Tunik

IPC: H01L23/00 ,  H01L23/535 ,  H01L21/768 ,  H10B20/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

CPC classification number: H01L23/562 ,  H01L21/7684 ,  H01L21/76895 ,  H01L23/535 ,  H10B20/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

Abstract: Disclosed is a three-dimensional memory device. In one embodiment, a device is disclosed comprising a source plate; plugs fabricated fabricated on or partially formed in the source plate; a stack formed on the substrate and plugs comprising alternating insulating layers and conductive layers and channel-material strings of memory cells extending through the insulating layers and conductive layers; a first set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates atop a respective plug in the plurality of plugs; and a second set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate.

公开(公告)号：US20220068956A1

公开(公告)日：2022-03-03

申请号：US17008130

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11565

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US20240021521A1

公开(公告)日：2024-01-18

申请号：US17812616

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Martin Jared Barclay ,  Harsh Narendrakumar Jain ,  Yiping Wang

IPC: H01L23/535 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L23/535 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11573

Abstract: Methods, systems, and devices for staircase structures for accessing three-dimensional (3D) memory arrays are described. A memory system may include an access region (e.g., a staircase region) that includes circuitry for accessing memory cells at respective levels of memory cells. The access region may include a channel through which a conductive pillar may couple a word line at a level of memory cells with decoder circuitry. During manufacture of the memory system, a channel material may be formed in the channel and etched to form a corner portion in the channel. During a partitioning of the channel, a nitride material over the corner portion may be etched and some of the corner portion may remain in the channel, which may prevent formation of a trench that may cause the conductive pillar to be uncoupled from the word line.

公开(公告)号：US20240128207A1

公开(公告)日：2024-04-18

申请号：US18542084

申请日：2023-12-15

Applicant: Micron Technology, Inc.

Inventor： Martin Jared Barclay ,  Mark Tunik

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/535 ,  H10B20/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

CPC classification number: H01L23/562 ,  H01L21/7684 ,  H01L21/76895 ,  H01L23/535 ,  H10B20/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

Abstract: Disclosed is a three-dimensional memory device. In one embodiment, a device is disclosed comprising a source plate; plugs fabricated on or partially formed in the source plate; a stack formed on the substrate and plugs comprising alternating insulating layers and conductive layers and channel-material strings of memory cells extending through the insulating layers and conductive layers; a first set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates atop a respective plug in the plurality of plugs; and a second set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate.

公开(公告)号：US20230117100A1

公开(公告)日：2023-04-20

申请号：US18083991

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lise M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H10B43/27 ,  H01L23/528 ,  H10B43/10 ,  H01L23/522 ,  H01L21/02 ,  H10B51/20 ,  H01L21/67

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US11532638B2

公开(公告)日：2022-12-20

申请号：US17008130

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11597 ,  H01L21/02 ,  H01L21/67 ,  G11C16/04

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US20240379544A1

公开(公告)日：2024-11-14

申请号：US18654618

申请日：2024-05-03

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Martin Jared Barclay ,  Haoyu Li

IPC: H01L23/528 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

Abstract: Methods, systems, and devices for low resistance staircase rivet contact using metal-to-metal strap connection are described. The described techniques provide for usage of a metallic material that adheres to a dielectric material when deposited via a chemical vapor deposition (CVD) process or atomic layer deposition (ALD) process to connect to a word line contact. For example, a strap may be formed between a layer of conductive material and a word line contact that extends at least partially through a stack of layers, and may be filled with such a metallic material. Such techniques may support a connection between the word line contact and the layer of conductive material without usage of a liner material, which may mitigate a resistance of the connection.