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1.发明公开公开(公告)号：US20240315040A1
公开(公告)日：2024-09-19
申请号：US18442547
申请日：2024-02-15
发明人： Akihiro TOBIOKA
CPC分类号： H10B43/50 , H01L23/5226 , H01L23/562 , H10B41/27 , H10B41/50 , H10B43/27
摘要： A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers. The alternating stacks are laterally spaced apart among one another by backside isolation assemblies. At least one of the backside isolation assemblies generally extends along a first horizontal direction with lateral undulations along a second horizontal direction that is perpendicular to the first horizontal direction. At least one of the alternating stacks has a modulation in width along the second horizontal direction as a function of a position along the first horizontal direction. Memory stack structures vertically extend through a respective one of the alternating stacks. Each of the backside isolation assemblies includes a respective laterally alternating sequence of backside dielectric isolation walls and backside dielectric support pillar structures.
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公开(公告)号：US20240215232A1
公开(公告)日：2024-06-27
申请号：US18428836
申请日：2024-01-31
发明人： Shuangqiang Luo , John D. Hopkins , Lifang Xu , Nancy M. Lomeli , Indra V. Chary , Kar Wui Thong , Shicong Wang
摘要： A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure has blocks separated from one another by first dielectric slot structures. Each of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of the tiers of the stack structure, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions. At least one second dielectric slot structure is within horizontal boundaries of the stadium structure in the first horizontal direction and partially vertically extends through and segmenting each of the two bridge regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
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公开(公告)号：US11997851B2
公开(公告)日：2024-05-28
申请号：US17004846
申请日：2020-08-27
发明人： Xiang Hui Zhao , Zui Xin Zeng , Jun Hu , Shi Zhang , Baoyou Chen
IPC分类号： H10B41/50 , H01L21/768 , H01L23/522 , H01L23/528 , H10B41/27 , H10B41/30 , H10B41/41 , H10B43/27 , H10B43/30 , H10B43/40 , H10B43/50 , H01L23/532
CPC分类号： H10B43/40 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H10B41/27 , H10B41/30 , H10B41/41 , H10B41/50 , H10B43/27 , H10B43/30 , H10B43/50 , H01L23/53209 , H01L23/53214 , H01L23/53242 , H01L23/53257 , H01L23/53271 , H01L23/5329
摘要： A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.
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公开(公告)号：US11963359B2
公开(公告)日：2024-04-16
申请号：US18199630
申请日：2023-05-19
摘要： Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US11961560B2
公开(公告)日：2024-04-16
申请号：US17096245
申请日：2020-11-12
发明人： Myunghun Lee , Sangwan Nam , Taemin Ok
IPC分类号： H01L23/528 , G11C16/04 , G11C16/26 , H10B41/27 , H10B41/40 , H10B41/50 , H10B43/10 , H10B43/20 , H10B43/27 , H10B43/40 , H10B43/50
CPC分类号： G11C16/0483 , G11C16/26 , H01L23/528 , H10B41/27 , H10B41/40 , H10B41/50 , H10B43/10 , H10B43/20 , H10B43/27 , H10B43/40 , H10B43/50
摘要： An integrated circuit device includes a peripheral circuit structure including a lower substrate, an arc protection diode in the lower substrate, and a common source line driver connected to the arc protection diode, a conductive plate on the peripheral circuit structure, a cell array structure overlapping the peripheral circuit structure in a vertical direction with the conductive plate therebetween, and a first wiring structure connected between the arc protection diode and the conductive plate.
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公开(公告)号：US11950418B2
公开(公告)日：2024-04-02
申请号：US17218117
申请日：2021-03-30
发明人： Xinxin Liu , Jingjing Geng , Zhu Yang , Chen Zuo , Xiangning Wang
摘要： Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device includes the following operations. A dielectric stack is formed to have interleaved sacrificial layers and dielectric layers. A stair is formed in the dielectric stack. The stair includes one or more sacrificial layers of the sacrificial layers and one or more dielectric layers of the dielectric layers. The stair exposes one of the sacrificial layers on a top surface and the one or more sacrificial layers on a side surface. An insulating portion is formed to cover the side surface of the stair to cover the one or more sacrificial layers. A sacrificial portion is formed to cover the top surface of the stair. The sacrificial portion is in contact with the one of sacrificial layers. The one or more sacrificial layers and the sacrificial portion are replaced with one or more conductor layers.
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公开(公告)号：US11910608B2
公开(公告)日：2024-02-20
申请号：US17961950
申请日：2022-10-07
申请人： Kioxia Corporation
发明人： Shinya Arai
IPC分类号： H10B43/27 , H10B41/27 , H10B43/40 , H01L21/764 , H01L29/06 , G11C16/14 , H10B41/35 , H10B41/50 , H10B43/35 , H10B43/50 , G11C16/04 , H01L21/311 , H01L21/3213 , H01L21/225 , H01L29/167 , H01L21/02 , H10B41/41
CPC分类号： H10B43/27 , G11C16/14 , H01L21/764 , H01L29/0649 , H10B41/27 , H10B41/35 , H10B41/50 , H10B43/35 , H10B43/40 , H10B43/50 , G11C16/0408 , G11C16/0466 , G11C16/0483 , H01L21/0217 , H01L21/2257 , H01L21/31116 , H01L21/32133 , H01L29/167 , H10B41/41
摘要： According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
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公开(公告)号：US11862573B2
公开(公告)日：2024-01-02
申请号：US16984962
申请日：2020-08-04
发明人： Martin Jared Barclay , Mark Tunik
IPC分类号： H01L23/00 , H01L23/535 , H01L21/768 , H10B20/00 , H10B41/10 , H10B41/27 , H10B41/50 , H10B43/10 , H10B43/27 , H10B43/50
CPC分类号： H01L23/562 , H01L21/7684 , H01L21/76895 , H01L23/535 , H10B20/00 , H10B41/10 , H10B41/27 , H10B41/50 , H10B43/10 , H10B43/27 , H10B43/50
摘要： Disclosed is a three-dimensional memory device. In one embodiment, a device is disclosed comprising a source plate; plugs fabricated fabricated on or partially formed in the source plate; a stack formed on the substrate and plugs comprising alternating insulating layers and conductive layers and channel-material strings of memory cells extending through the insulating layers and conductive layers; a first set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates atop a respective plug in the plurality of plugs; and a second set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate.
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公开(公告)号：US11805655B2
公开(公告)日：2023-10-31
申请号：US17324411
申请日：2021-05-19
发明人： Donghoon Kwon , Junsuk Kim , Jongheun Lim
IPC分类号： H01L21/00 , H10B43/50 , H01L23/535 , H01L21/768 , H10B41/27 , H10B41/41 , H10B41/50 , H10B43/27 , H10B43/40
CPC分类号： H10B43/50 , H01L21/76805 , H01L21/76895 , H01L23/535 , H10B41/27 , H10B41/41 , H10B41/50 , H10B43/27 , H10B43/40
摘要： A memory device includes a cell stacked structure on a substrate, the cell stacked structure including insulation layers and gate patterns alternately stacked, a channel structure passing through the cell stacked structure, the channel structure extending in a vertical direction, a dummy structure on the substrate, the dummy structure being spaced apart from the cell stacked structure, and the dummy structure including insulation layers and metal patterns alternately stacked, a first through via contact passing through the dummy structure, the first through via contact extending in the vertical direction, and a first capping insulation pattern between a sidewall of the first through via contact and each of the metal patterns in the dummy structure, the first capping insulation pattern insulating the first through via contact from each of the metal patterns.
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公开(公告)号：US11716848B2
公开(公告)日：2023-08-01
申请号：US17126777
申请日：2020-12-18
摘要： Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.
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