公开(公告)号：US20240403177A1

公开(公告)日：2024-12-05

申请号：US18678557

申请日：2024-05-30

Applicant: Micron Technology, Inc.

Inventor： Su Wei Lim ,  Senthil Murugan Thangaraj ,  Marco Sforzin ,  Daniele Balluchi ,  Massimiliano Patriarca ,  Giorgio Servalli ,  Angelo Visconti ,  Antonino Capri’ ,  Garth N. Grubb ,  Amitava Majumdar ,  Miguel Mares

IPC: G06F11/20 ,  G06F11/14

Abstract: Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.