公开(公告)号：US11023173B2

公开(公告)日：2021-06-01

申请号：US16559497

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Ming-Bo Liu

IPC: G06F3/06 ,  G11C7/10 ,  G06F11/10 ,  G11C8/10

Abstract: An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.

公开(公告)号：US10418090B1

公开(公告)日：2019-09-17

申请号：US16014539

申请日：2018-06-21

Applicant: Micron Technology, Inc.

Inventor： Ming-Bo Liu ,  Daniel B. Penney

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: Systems and methods include capture circuitry configured to capture a write signal from a host device using a data strobe signal from the host device and to output one or more indications of capture of the write signal. Calculation circuitry is configured to receive the data strobe signal, receive the one or more indications of capture, and determine a delay between a first edge of the data strobe signal and receipt of the one or more indications of capture. The systems and methods also include transmission and control circuitry configured to launch subsequent write signals at a time based at least in part on the delay.

公开(公告)号：US10679683B1

公开(公告)日：2020-06-09

申请号：US16825096

申请日：2020-03-20

Applicant: Micron Technology, Inc.

Inventor： Liang Chen ,  Ming-Bo Liu

IPC: G11C7/04 ,  G11C7/22 ,  G06F13/18 ,  H04L25/03 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4074 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4093 ,  G11C11/4076

Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device. A walk back circuit is provided to mimic propagation delays of an internal command signal, such as a write command signal, and to speed up the delayed internal command signal an amount equivalent to the propagation delays. The walk back circuit includes a mixture of delay elements provided to mimic propagation delays caused by both gate delays and routing delays.

公开(公告)号：US11056171B1

公开(公告)日：2021-07-06

申请号：US16737727

申请日：2020-01-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Kangjoo Lee ,  Ming-Bo Liu

IPC: G11C11/407 ,  G11C11/409 ,  G11C11/4076 ,  G11C11/4093

Abstract: Apparatuses and methods for wide clock frequency range command paths are disclosed. An example apparatus includes a command decoder and a command timing circuit. The command decoder is configured to receive a command and is further configured to decode the command to provide a decoded command. The command timing circuit is configured to receive the decoded command responsive to a clock and is further configured to provide a delayed internal command having a delay relative to receiving the decoded command based on clock frequency information indicative of a clock frequency of the clock. The command timing circuit includes a plurality of command timing paths. Each of the plurality of command timing paths is configured to provide a respective delay to the decoded command for a respective range of clock frequencies.

公开(公告)号：US20210201978A1

公开(公告)日：2021-07-01

申请号：US16737727

申请日：2020-01-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Kangjoo Lee ,  Ming-Bo Liu

IPC: G11C11/4076 ,  G11C11/4093

Abstract: Apparatuses and methods for wide clock frequency range command paths are disclosed. An example apparatus includes a command decoder and a command timing circuit. The command decoder is configured to receive a command and is further configured to decode the command to provide a decoded command. The command timing circuit is configured to receive the decoded command responsive to a clock and is further configured to provide a delayed internal command having a delay relative to receiving the decoded command based on clock frequency information indicative of a clock frequency of the clock. The command timing circuit includes a plurality of command timing paths. Each of the plurality of command timing paths is configured to provide a respective delay to the decoded command for a respective range of clock frequencies.

公开(公告)号：US20190259442A1

公开(公告)日：2019-08-22

申请号：US15955330

申请日：2018-04-17

Applicant: Micron Technology, Inc.

Inventor： Liang Chen ,  Ming-Bo Liu

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device. A walk back circuit is provided to mimic propagation delays of an internal command signal, such as a write command signal, and to speed up the delayed internal command signal an amount equivalent to the propagation delays. The walk back circuit includes a mixture of delay elements provided to mimic propagation delays caused by both gate delays and routing delays.

公开(公告)号：US11544010B2

公开(公告)日：2023-01-03

申请号：US17332909

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Ming-Bo Liu

IPC: H03M13/09 ,  H04L1/00 ,  G06T1/20 ,  G06F9/50 ,  G06F3/06 ,  G11C7/10 ,  G06F11/10 ,  G11C8/10

Abstract: An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.

公开(公告)号：US20210294533A1

公开(公告)日：2021-09-23

申请号：US17332909

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Ming-Bo Liu

IPC: G06F3/06 ,  G11C7/10 ,  G06F11/10 ,  G11C8/10

Abstract: An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.

公开(公告)号：US20210064282A1

公开(公告)日：2021-03-04

申请号：US16559497

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Ming-Bo Liu

IPC: G06F3/06 ,  G11C7/10 ,  G11C8/10 ,  G06F11/10

Abstract: An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.

公开(公告)号：US10803924B2

公开(公告)日：2020-10-13

申请号：US16514819

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Ming-Bo Liu ,  Daniel B. Penney

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: Systems and methods include capture circuitry configured to capture a write signal from a host device using a data strobe signal from the host device and to output one or more indications of capture of the write signal. Calculation circuitry is configured to receive the data strobe signal, receive the one or more indications of capture, and determine a delay between a first edge of the data strobe signal and receipt of the one or more indications of capture. The systems and methods also include transmission and control circuitry configured to launch subsequent write signals at a time based at least in part on the delay.