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公开(公告)号：US12068021B2
公开(公告)日：2024-08-20
申请号：US17746757
申请日：2022-05-17
IPC分类号： G11C11/4076 , G11C11/4093
CPC分类号： G11C11/4076 , G11C11/4093
摘要： An exemplary semiconductor device includes an internal clock circuit configured to intermittently enable and disable a clock signal while in a Maximum Power Savings Mode. The duty cycle of the enablement and disablement of the clock signal may be based on susceptibility to negative-bias temperature instability of a component of the semiconductor device. The clock signal may be enabled and disabled via a synchronizer.
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公开(公告)号：US20240168678A1
公开(公告)日：2024-05-23
申请号：US18478893
申请日：2023-09-29
IPC分类号： G06F3/06 , G06F11/263
CPC分类号： G06F3/0656 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G06F11/263
摘要： Methods, systems, and devices for techniques for performing write operations are described. A controller of a memory system may generate a first command to write first data to a first set of memory cells of a memory array of the memory system. The controller may transmit the first command to a first buffer of the memory system. The first buffer may receive the first command and may generate the first data based on second data from a first address of a register. The first buffer may transmit the first data to the first set of memory cells, via a first buffer, based on the first command.
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公开(公告)号：US20230076261A1
公开(公告)日：2023-03-09
申请号：US17466052
申请日：2021-09-03
IPC分类号： G11C7/10 , G11C11/4096 , G11C7/22 , G11C11/4076
摘要： Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.
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公开(公告)号：US10825492B2
公开(公告)日：2020-11-03
申请号：US16416425
申请日：2019-05-20
发明人： Debra Bell , Kallol Mazumder
摘要： Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.
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公开(公告)号：US10607681B2
公开(公告)日：2020-03-31
申请号：US16022378
申请日：2018-06-28
发明人： Kallol Mazumder
IPC分类号： G11C11/406 , G11C11/4076 , G11C11/409
摘要： An apparatus may include a semiconductor device that includes an internal clock circuit configured to receive an internal clock signal and to provide a local clock signal based on the internal clock signal. The internal clock circuit comprises a clock synchronizer configured to, in response to receipt of a command to exit a self-refresh mode, disable provision of the local clock signal by a number of cycles of the internal clock signal.
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公开(公告)号：US10354717B1
公开(公告)日：2019-07-16
申请号：US15976698
申请日：2018-05-10
发明人： Jason M. Brown , Vijayakrishna J. Vankayala , William C. Waldrop , Kallol Mazumder , Byung S. Moon , Ravi Kiran Kandikonda
IPC分类号： G11C11/4076 , G11C11/4093 , G06F11/10 , G11C11/4096
摘要： Aspects of the present disclosure eliminating the need for a memory device to have both a shifter that shifts input pin values from an input domain into a parity domain and another shifter that shifts a decoded command from the input domain into the parity domain. A memory device can achieve this by, when parity is being performed, shifting the input from the input pins into the parity domain prior to decoding the command. Using a multiplexer, the decoder can receive the command pin portion of the shifted input when parity checking is being performed and can receive the un-shifted command pin input when parity checking is not being performed. The decoder can use the command pin portion of the shifted input to generate shifted and decoded commands or can use the un-shifted command pin input to generate decoded commands.
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公开(公告)号：US10312919B2
公开(公告)日：2019-06-04
申请号：US16105836
申请日：2018-08-20
发明人： Kallol Mazumder
摘要： Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.
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公开(公告)号：US20190020342A1
公开(公告)日：2019-01-17
申请号：US16013813
申请日：2018-06-20
发明人： Kallol Mazumder
IPC分类号： H03K19/0175 , H03K3/037 , G11C11/4076
摘要： A semiconductor device includes a clock divider that receives a clock signal and generates even and odd clock signals. The clock signal includes a first frequency, while the even and odd clock signals each includes a second frequency that is half the first frequency. The semiconductor device also includes even and odd command paths coupled to the clock divider each having a set of logic and a set of flip-flops. The even command path receives a command and the even clock signal and outputs an even output signal. The odd command path receives the command and the odd clock signal and outputs an odd output signal. The semiconductor device also includes combination circuitry coupled to the even and odd command paths that combines the even and odd output signals.
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公开(公告)号：US20180358971A1
公开(公告)日：2018-12-13
申请号：US16105836
申请日：2018-08-20
发明人： Kallol Mazumder
摘要： Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.
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公开(公告)号：US10153014B1
公开(公告)日：2018-12-11
申请号：US15680006
申请日：2017-08-17
发明人： Kallol Mazumder
IPC分类号： G11C7/00 , G11C7/10 , G11C11/4063 , H03K19/003 , H03K19/0175 , G11C7/22 , G11C29/02
摘要： Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin (DQ) during the read operation. An input, such as a mode register, receives an indication of a shift mode register value that corresponds to a number of shifts of a rising edge of the command in a backward or a falling edge in a forward direction. A delay chain delays the appropriate edge of received command the number of shifts in the corresponding direction to generate a shifted edge command signal. Combination circuitry then combines a falling edge command signal with a shifted rising edge command signal to form a transformed command.
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