公开(公告)号：US20250006243A1

公开(公告)日：2025-01-02

申请号：US18829734

申请日：2024-09-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuan He ,  Takamasa Suzuki

IPC: G11C11/406 ,  G11C11/408

Abstract: Apparatuses, systems, and methods for access based targeted refresh operations. A memory bank has a first sub-bank and a second sub-bank. A refresh control circuit detects an aggressor in one of the sub-banks. Responsive to an access in the other sub-bank, the refresh control circuit performs a targeted refresh operation based on the sub-bank based on the aggressor address.

公开(公告)号：US12113015B2

公开(公告)日：2024-10-08

申请号：US17396341

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Yuan He

IPC: H01L23/525 ,  G11C29/00 ,  H10B12/00 ,  G11C11/4096

CPC classification number: H01L23/5256 ,  H10B12/50 ,  G11C11/4096

Abstract: Methods, systems, and devices for vertical transistor fuse latches are described. An apparatus may include a substrate and a memory array that is coupled with the substrate. The apparatus may also include a latch that is configured to store information from a fuse for the memory array. The latch may be at least partially within an additional substrate separate from and above the substrate. The latch may include a quantity of p-type vertical transistors and a quantity of n-type vertical transistors each at least partially disposed within the additional substrate above the substrate.

公开(公告)号：US12105984B2

公开(公告)日：2024-10-01

申请号：US17005290

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Pu Yang

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: An exemplary register circuit includes a plurality of slots to store respective addresses and data pairs. During a write operation, each slot of a plurality of slots preceding a particular slot of the plurality of slots indicated as empty is shifted by one slot to fill the particular slot such that a first end slot of the plurality of slots is made available to receive a new write address and data pair. Each slot of the plurality of slots subsequent to the particular slot retains existing address and data pairs.

公开(公告)号：US20240071473A1

公开(公告)日：2024-02-29

申请号：US17898150

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Fatma Arzum Simsek-Ege

IPC: G11C11/4091 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C11/4085

Abstract: A microelectronic device is disclosed that incudes array regions individually comprising memory cells comprising access devices and storage node devices; digit lines coupled to the access devices that extend in a first direction; and word lines coupled to the access devices that extend in a second direction orthogonal to the first direction. Digit line exit regions horizontally alternate with the array regions in the first direction; sense amplifier sections comprising sense amplifier circuitry vertically overlie and horizontally overlapping the digit line exit regions; and routing structures within horizontal areas of the digit line exit regions, couple the sense amplifier circuitry of the sense amplifier sections to the digit lines.

公开(公告)号：US11804260B2

公开(公告)日：2023-10-31

申请号：US17746542

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Tae H. Kim

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/4096 ,  H03K19/173 ,  G11C5/06 ,  G11C11/404

CPC classification number: G11C11/4091 ,  G11C5/06 ,  G11C11/4045 ,  G11C11/4096 ,  H03K19/1737

Abstract: A sense amplifier can be formed outside of/horizontally adjacent to an array of vertically stacked tiers of memory cells. Memory cells can be sensed via multiplexors formed under the array that can operate to couple vertical sense lines (to which the memory cells are coupled) to horizontal sense lines (to which the sense amplifier is coupled).

公开(公告)号：US11777488B2

公开(公告)日：2023-10-03

申请号：US17656397

申请日：2022-03-24

Applicant: Micron Technology, Inc.

Inventor： Hiroshi Akamatsu ,  Yuan He ,  Toru Ishikawa

IPC: G06F13/40 ,  H03K17/16 ,  G11C7/10

CPC classification number: H03K17/161 ,  G06F13/4077 ,  G11C7/1048

Abstract: Charge transfer between gate terminals of sub-threshold current reduction circuit (SCRC) transistors and related apparatuses and methods are disclosed. An apparatus includes a first output terminal electrically connected to a pull-up gate terminal of at least one pull-up SCRC transistor and a second output terminal electrically connected to a pull-down gate terminal of at least one pull-down SCRC transistor. The apparatus also includes a first resistive path between a first input terminal and the first output terminal and a second resistive path between the second input terminal and the second output terminal. The apparatus further includes a charge transfer gate electrically connected between the first resistive path and the second resistive path.

公开(公告)号：US20230207505A1

公开(公告)日：2023-06-29

申请号：US17562453

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Yuan He

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L27/108 ,  G11C11/408 ,  G11C11/4091

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/80 ,  H01L25/50 ,  H01L27/10805 ,  H01L27/10897 ,  G11C11/4085 ,  G11C11/4091 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A microelectronic device comprises a microelectronic device comprises a first microelectronic device structure comprising a stack structure comprising conductive structures vertically alternating with insulative structures, a staircase structure within the stack structure, and vertical stacks of memory cells. Each vertical stack of memory cells individually comprises a vertical stack of capacitor structures, transistor structures each individually neighboring a capacitor structure of the capacitor structures, and a conductive pillar structure vertically extending through the transistor structures. The microelectronic device further comprises a second microelectronic device structure attached to the first microelectronic device structure, the second microelectronic device structure comprising a sub word line driver region comprising complementary metal-oxide-semiconductor (CMOS) circuits vertically overlying and within a horizontal area of the staircase structure, and conductive contact structures vertically extending between steps of the staircase structure and the sub word line driver region. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20230206989A1

公开(公告)日：2023-06-29

申请号：US17565187

申请日：2021-12-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuan He ,  Dong Pan

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/406

CPC classification number: G11C11/4082 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4087 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/40611

Abstract: Apparatuses and methods for row hammer counter mat. A memory array may have a number of memory mats and a counter memory mat. The counter mat stores count values, each of which is associated with a row in one of the other memory mats. When a row is accessed, the count value is read out, changed, and written back to the counter mat. In some embodiments, the count value may be processed within access logic of the counter mat, and a row hammer flag may be provided to the bank logic. In some embodiments, the counter mat may have a folded architecture where each sense amplifier is coupled to multiple bit lines in the counter mat. The count value may be used to determine if the accessed row is an aggressor so that its victims can be refreshed as part of a targeted refresh.

公开(公告)号：US11587931B2

公开(公告)日：2023-02-21

申请号：US17190705

申请日：2021-03-03

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Fatma Arzum Simsek-Ege

IPC: G11C5/00 ,  H01L27/108 ,  G11C11/4096 ,  G11C11/4091 ,  H01L27/06 ,  G11C5/10 ,  G11C11/402

Abstract: A memory device can comprise an array of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers, and a plurality of vertical sense lines coupled to each of the plurality of tiers. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line and configured to electrically couple the respective vertical sense line to a horizontal sense line. The memory device can also comprise a semiconductor under the array (SuA) circuitry, comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.

公开(公告)号：US20230029528A1

公开(公告)日：2023-02-02

申请号：US17385340

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Takehiro Hasegawa ,  Chikara Kondo ,  Yuan He ,  Hyunui Lee

IPC: G11C29/12 ,  G11C7/22

Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a data signal according to a clock signal to obtain a data sample; sampling the data signal according to an advanced clock signal to obtain an advanced data sample; and sampling the data signal according to a delayed clock signal to obtain a delayed data sample. The method may also include comparing the data sample with the advanced data sample and the delayed data sample and performing an action based on the comparison. The action may include selecting a data sample, selecting a clock signal and/or adjusting a clock signal. Associated devices and systems are also disclosed.