公开(公告)号：US20240268118A1

公开(公告)日：2024-08-08

申请号：US18435116

申请日：2024-02-07

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Patrick White ,  Kevin Y. Titus ,  Steven P. Turini

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/67 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L21/0217 ,  H01L21/67063 ,  H10B43/35 ,  H10B43/40

Abstract: A method used in forming memory circuitry comprises forming a stack where strings of memory cells will be formed and a select-gate region directly above the stack. The stack comprises vertically-alternating different-composition first tiers and second tiers having lower channel openings extending there-through. The select-gate region comprises upper channel openings extending there-through and that are individually directly above and extend to individual of the lower channel openings. Storage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. Then, insulative charge-passage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. Then, channel material is formed simultaneously in the upper and lower channel openings. The storage material is removed from the upper channel openings. After the removing, a select gate is formed in the select-gate region operatively aside the channel material in the select-gate region. Other embodiments, including structure, are disclosed.