公开(公告)号：US20240268118A1

公开(公告)日：2024-08-08

申请号：US18435116

申请日：2024-02-07

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Patrick White ,  Kevin Y. Titus ,  Steven P. Turini

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/67 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L21/0217 ,  H01L21/67063 ,  H10B43/35 ,  H10B43/40

Abstract: A method used in forming memory circuitry comprises forming a stack where strings of memory cells will be formed and a select-gate region directly above the stack. The stack comprises vertically-alternating different-composition first tiers and second tiers having lower channel openings extending there-through. The select-gate region comprises upper channel openings extending there-through and that are individually directly above and extend to individual of the lower channel openings. Storage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. Then, insulative charge-passage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. Then, channel material is formed simultaneously in the upper and lower channel openings. The storage material is removed from the upper channel openings. After the removing, a select gate is formed in the select-gate region operatively aside the channel material in the select-gate region. Other embodiments, including structure, are disclosed.

公开(公告)号：US20240357837A1

公开(公告)日：2024-10-24

申请号：US18642555

申请日：2024-04-22

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Stephen W. Russell ,  Steven P. Turini ,  Farrell M. Good ,  Kolya Yastrebenetsky ,  Nirav Vora ,  Zhao Zhao

IPC: H10B63/00 ,  H10B63/10

CPC classification number: H10B63/845 ,  H10B63/10

Abstract: Methods, systems, and devices for contact formation for a memory device are described. A memory device manufacturing operation may include forming bit lines and word lines in a same step. In some cases, the memory device may include word line contact portions that couple respective word lines with respective word line contacts located below the word lines. For example, the word line contact portions may be located between word lines and a substrate of the memory array. In such cases, the processing step may be used for formation of word lines, bit lines, and word line contact portions. Additionally, or alternatively, the memory device manufacturing operation may include forming a sacrificial ring around bit line contacts, which may isolate bit line contacts from a nitride layer.