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1.发明授权公开(公告)号：US11815935B2
公开(公告)日：2023-11-14
申请号：US17705099
申请日：2022-03-25
Applicant: Micron Technology, Inc.
Inventor： Skyler Arron Windh , Allan Kennedy Porterfield , Douglas John Vanesko , Randall Paul Meyer , Patrick Alan Estep , Bashar Romanous
IPC: G06F8/41
Abstract: An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.
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2.发明公开公开(公告)号：US20230315415A1
公开(公告)日：2023-10-05
申请号：US17705099
申请日：2022-03-25
Applicant: Micron Technology, Inc.
Inventor： Skyler Arron Windh , Allan Kennedy Porterfield , Douglas John Vanesko , Randall Paul Meyer , Patrick Alan Estep , Bashar Romanous
IPC: G06F8/41
Abstract: An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.
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