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公开(公告)号：US12039335B2
公开(公告)日：2024-07-16
申请号：US17705112
申请日：2022-03-25
Applicant: Micron Technology, Inc.
Inventor： Allan Kennedy Porterfield , Skyler Arron Windh , Bashar Romanous
IPC: G06F9/30
CPC classification number: G06F9/30181 , G06F9/30043
Abstract: Schedule instructions of a program for execution on a coarse grained reconfigurable array having a plurality of tiles operable in parallel. The program identifies data flows through memory locations represented by memory variables and identifies instructions configured to transform data in the data flows. Based on a hardware profile identifying features of the coarse grained reconfigurable array, a scheduler is configured to generate a memory map. The memory map identifies, for each respective memory variable in the program, one of the tiles that contains a memory location represented by the respective memory variable. Based on the memory map reducing possible choices for a brute force search, the scheduler assigns the instructions to the tiles for execution, and determines timing of execution of the instructions in the tiles.
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2.发明授权公开(公告)号：US11815935B2
公开(公告)日：2023-11-14
申请号：US17705099
申请日：2022-03-25
Applicant: Micron Technology, Inc.
Inventor： Skyler Arron Windh , Allan Kennedy Porterfield , Douglas John Vanesko , Randall Paul Meyer , Patrick Alan Estep , Bashar Romanous
IPC: G06F8/41
Abstract: An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.
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公开(公告)号：US20230306272A1
公开(公告)日：2023-09-28
申请号：US18185031
申请日：2023-03-16
Applicant: Micron Technology, Inc.
Inventor： Andre Xian Ming Chang , Abhishek Chaurasia , Parth Khopkar , Bashar Romanous , Patrick Alan Estep , Skyler Arron Windh , Eugenio Culurciello , Sheik Dawood Beer Mohideen
Abstract: An artificial neural network is trained via reinforcement learning to receive first data representative of execution dependency conditions of instructions of a program, second data representative of a schedule of a first portion of the instructions of the program for execution in a device having a plurality of circuits units operable in parallel, and third data identifying a next instruction selected from a second portion of the instructions of the program remaining to be scheduled for execution in the device. The artificial neural network selects a placement of the next instruction in one of the circuit units from a plurality of possible placements of the next instruction in the device. Performance of placements of instructions being tested in search for a valid schedule for running the program in the device can be measured to generate samples to train the artificial neural network via reinforcement learning.
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Patent Agency Ranking
公开(公告)号：US20250021317A1
公开(公告)日：2025-01-16
申请号：US18768477
申请日：2024-07-10
Applicant: Micron Technology, Inc.
Inventor： Bashar Romanous , Skyler Arron Windh , Patrick Estep
IPC: G06F8/41
Abstract: Devices and techniques for parallelizing loops that have loop-dependent variables are described herein. A system includes a processing device; and a memory device configured to store instructions, which when executed by the processing device, cause the processing device to perform operations comprising: accessing, by a compiler executing on a processing device, a computer code listing; determining that the computer code listing includes a loop with a loop-carried dependency variable; optimizing the loop for parallel execution by removing the loop-carried dependency variable; and compiling the computer code listing into executable software code with the loop executable in parallel in hardware.
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5.发明公开公开(公告)号：US20240362024A1
公开(公告)日：2024-10-31
申请号：US18770560
申请日：2024-07-11
Applicant: Micron Technology, Inc.
Inventor： Allan Kennedy Porterfield , Skyler Arron Windh , Bashar Romanous
IPC: G06F9/30
CPC classification number: G06F9/30181 , G06F9/30043
Abstract: Schedule instructions of a program for execution on a coarse grained reconfigurable array having a plurality of tiles operable in parallel. The program identifies data flows through memory locations represented by memory variables and identifies instructions configured to transform data in the data flows. Based on a hardware profile identifying features of the coarse grained reconfigurable array, a scheduler is configured to generate a memory map. The memory map identifies, for each respective memory variable in the program, one of the tiles that contains a memory location represented by the respective memory variable. Based on the memory map reducing possible choices for a brute force search, the scheduler assigns the instructions to the tiles for execution, and determines timing of execution of the instructions in the tiles.
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公开(公告)号：US20240354121A1
公开(公告)日：2024-10-24
申请号：US18590449
申请日：2024-02-28
Applicant: Micron Technology, Inc.
Inventor： Bashar Romanous , Patrick Alan Estep , Skyler Arron Windh
CPC classification number: G06F9/44505 , G06F11/3409
Abstract: An exploration tool of a design space of configurations to execute a data flow program using circuit tiles of a coarse grained reconfigurable array. The tool can identify different configurations for the program and determine performance metrics of the configurations. A user of the tool can provide one or more criteria in a request to the tool; and in response, the tool can identify, from the different configurations and based on the one or more criteria applied to the performance metrics, a first configuration of executing the program on the coarse grained reconfigurable array. For example, the tool can use a toolchain to generate the configurations and use a simulator to run simulations of executions of the program according to the configurations. The tool can compare attributes determined by the toolchain and the simulator for consistency in detecting errors or defects in the toolchain and the simulator.
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7.发明公开公开(公告)号：US20230315415A1
公开(公告)日：2023-10-05
申请号：US17705099
申请日：2022-03-25
Applicant: Micron Technology, Inc.
Inventor： Skyler Arron Windh , Allan Kennedy Porterfield , Douglas John Vanesko , Randall Paul Meyer , Patrick Alan Estep , Bashar Romanous
IPC: G06F8/41
Abstract: An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.
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8.发明公开公开(公告)号：US20230305848A1
公开(公告)日：2023-09-28
申请号：US17705112
申请日：2022-03-25
Applicant: Micron Technology, Inc.
Inventor： Allan Kennedy Porterfield , Skyler Arron Windh , Bashar Romanous
IPC: G06F9/30
CPC classification number: G06F9/30181 , G06F9/30043
Abstract: Schedule instructions of a program for execution on a coarse grained reconfigurable array having a plurality of tiles operable in parallel. The program identifies data flows through memory locations represented by memory variables and identifies instructions configured to transform data in the data flows. Based on a hardware profile identifying features of the coarse grained reconfigurable array, a scheduler is configured to generate a memory map. The memory map identifies, for each respective memory variable in the program, one of the tiles that contains a memory location represented by the respective memory variable. Based on the memory map reducing possible choices for a brute force search, the scheduler assigns the instructions to the tiles for execution, and determines timing of execution of the instructions in the tiles.
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