公开(公告)号：US20240354121A1

公开(公告)日：2024-10-24

申请号：US18590449

申请日：2024-02-28

Applicant: Micron Technology, Inc.

Inventor： Bashar Romanous ,  Patrick Alan Estep ,  Skyler Arron Windh

IPC: G06F9/445 ,  G06F11/34

CPC classification number: G06F9/44505 ,  G06F11/3409

Abstract: An exploration tool of a design space of configurations to execute a data flow program using circuit tiles of a coarse grained reconfigurable array. The tool can identify different configurations for the program and determine performance metrics of the configurations. A user of the tool can provide one or more criteria in a request to the tool; and in response, the tool can identify, from the different configurations and based on the one or more criteria applied to the performance metrics, a first configuration of executing the program on the coarse grained reconfigurable array. For example, the tool can use a toolchain to generate the configurations and use a simulator to run simulations of executions of the program according to the configurations. The tool can compare attributes determined by the toolchain and the simulator for consistency in detecting errors or defects in the toolchain and the simulator.

公开(公告)号：US20230315415A1

公开(公告)日：2023-10-05

申请号：US17705099

申请日：2022-03-25

Applicant: Micron Technology, Inc.

Inventor： Skyler Arron Windh ,  Allan Kennedy Porterfield ,  Douglas John Vanesko ,  Randall Paul Meyer ,  Patrick Alan Estep ,  Bashar Romanous

IPC: G06F8/41

CPC classification number: G06F8/453 ,  G06F8/433 ,  G06F8/451 ,  G06F8/457 ,  G06F8/458

Abstract: An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

公开(公告)号：US20240428853A1

公开(公告)日：2024-12-26

申请号：US18825829

申请日：2024-09-05

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  Patrick Alan Estep ,  David Andrew Roberts

IPC: G11C11/54 ,  G06F12/0862 ,  G06F12/0897 ,  G06N3/063 ,  G06N3/08

Abstract: Systems, devices, and methods related to a deep learning accelerator and memory are described. For example, the accelerator can have processing units to perform at least matrix computations of an artificial neural network via execution of instructions. The processing units have a local memory store operands of the instructions. The accelerator can access a random access memory via a system buffer, or without going through the system buffer. A fetch instruction can request an item, available at a memory address in the random access memory, to be loaded into the local memory at a local address. The fetch instruction can include a hint for the caching of the item in the system buffer. During execution of the instruction, the hint can be used to determine whether to load the item through the system buffer or to bypass the system buffer in loading the item.

公开(公告)号：US12094531B2

公开(公告)日：2024-09-17

申请号：US17146314

申请日：2021-01-11

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  Patrick Alan Estep ,  David Andrew Roberts

IPC: G06F3/06 ,  G06F12/0862 ,  G06F12/0897 ,  G06N3/063 ,  G06N3/08 ,  G11C11/54

CPC classification number: G11C11/54 ,  G06F12/0862 ,  G06F12/0897 ,  G06N3/063 ,  G06N3/08

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, the accelerator can have processing units to perform at least matrix computations of an artificial neural network via execution of instructions. The processing units have a local memory store operands of the instructions. The accelerator can access a random access memory via a system buffer, or without going through the system buffer. A fetch instruction can request an item, available at a memory address in the random access memory, to be loaded into the local memory at a local address. The fetch instruction can include a hint for the caching of the item in the system buffer. During execution of the instruction, the hint can be used to determine whether to load the item through the system buffer or to bypass the system buffer in loading the item.

公开(公告)号：US11815935B2

公开(公告)日：2023-11-14

申请号：US17705099

申请日：2022-03-25

Applicant: Micron Technology, Inc.

Inventor： Skyler Arron Windh ,  Allan Kennedy Porterfield ,  Douglas John Vanesko ,  Randall Paul Meyer ,  Patrick Alan Estep ,  Bashar Romanous

IPC: G06F8/41

CPC classification number: G06F8/453 ,  G06F8/433 ,  G06F8/451 ,  G06F8/457 ,  G06F8/458

Abstract: An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

公开(公告)号：US20230306272A1

公开(公告)日：2023-09-28

申请号：US18185031

申请日：2023-03-16

Applicant: Micron Technology, Inc.

Inventor： Andre Xian Ming Chang ,  Abhishek Chaurasia ,  Parth Khopkar ,  Bashar Romanous ,  Patrick Alan Estep ,  Skyler Arron Windh ,  Eugenio Culurciello ,  Sheik Dawood Beer Mohideen

IPC: G06N3/092 ,  G06N3/045 ,  G06N3/10

CPC classification number: G06N3/092 ,  G06N3/045 ,  G06N3/10

Abstract: An artificial neural network is trained via reinforcement learning to receive first data representative of execution dependency conditions of instructions of a program, second data representative of a schedule of a first portion of the instructions of the program for execution in a device having a plurality of circuits units operable in parallel, and third data identifying a next instruction selected from a second portion of the instructions of the program remaining to be scheduled for execution in the device. The artificial neural network selects a placement of the next instruction in one of the circuit units from a plurality of possible placements of the next instruction in the device. Performance of placements of instructions being tested in search for a valid schedule for running the program in the device can be measured to generate samples to train the artificial neural network via reinforcement learning.

公开(公告)号：US20220223201A1

公开(公告)日：2022-07-14

申请号：US17146314

申请日：2021-01-11

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  Patrick Alan Estep ,  David Andrew Roberts

IPC: G11C11/54 ,  G06N3/063 ,  G06N3/08 ,  G06F12/0862 ,  G06F12/0897

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, the accelerator can have processing units to perform at least matrix computations of an artificial neural network via execution of instructions. The processing units have a local memory store operands of the instructions. The accelerator can access a random access memory via a system buffer, or without going through the system buffer. A fetch instruction can request an item, available at a memory address in the random access memory, to be loaded into the local memory at a local address. The fetch instruction can include a hint for the caching of the item in the system buffer. During execution of the instruction, the hint can be used to determine whether to load the item through the system buffer or to bypass the system buffer in loading the item.