公开(公告)号：US11815935B2

公开(公告)日：2023-11-14

申请号：US17705099

申请日：2022-03-25

Applicant: Micron Technology, Inc.

Inventor： Skyler Arron Windh ,  Allan Kennedy Porterfield ,  Douglas John Vanesko ,  Randall Paul Meyer ,  Patrick Alan Estep ,  Bashar Romanous

IPC: G06F8/41

CPC classification number: G06F8/453 ,  G06F8/433 ,  G06F8/451 ,  G06F8/457 ,  G06F8/458

Abstract: An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

公开(公告)号：US20240362024A1

公开(公告)日：2024-10-31

申请号：US18770560

申请日：2024-07-11

Applicant: Micron Technology, Inc.

Inventor： Allan Kennedy Porterfield ,  Skyler Arron Windh ,  Bashar Romanous

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F9/30043

Abstract: Schedule instructions of a program for execution on a coarse grained reconfigurable array having a plurality of tiles operable in parallel. The program identifies data flows through memory locations represented by memory variables and identifies instructions configured to transform data in the data flows. Based on a hardware profile identifying features of the coarse grained reconfigurable array, a scheduler is configured to generate a memory map. The memory map identifies, for each respective memory variable in the program, one of the tiles that contains a memory location represented by the respective memory variable. Based on the memory map reducing possible choices for a brute force search, the scheduler assigns the instructions to the tiles for execution, and determines timing of execution of the instructions in the tiles.

公开(公告)号：US12039335B2

公开(公告)日：2024-07-16

申请号：US17705112

申请日：2022-03-25

Applicant: Micron Technology, Inc.

Inventor： Allan Kennedy Porterfield ,  Skyler Arron Windh ,  Bashar Romanous

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F9/30043

Abstract: Schedule instructions of a program for execution on a coarse grained reconfigurable array having a plurality of tiles operable in parallel. The program identifies data flows through memory locations represented by memory variables and identifies instructions configured to transform data in the data flows. Based on a hardware profile identifying features of the coarse grained reconfigurable array, a scheduler is configured to generate a memory map. The memory map identifies, for each respective memory variable in the program, one of the tiles that contains a memory location represented by the respective memory variable. Based on the memory map reducing possible choices for a brute force search, the scheduler assigns the instructions to the tiles for execution, and determines timing of execution of the instructions in the tiles.

公开(公告)号：US20230315415A1

公开(公告)日：2023-10-05

申请号：US17705099

申请日：2022-03-25

Applicant: Micron Technology, Inc.

Inventor： Skyler Arron Windh ,  Allan Kennedy Porterfield ,  Douglas John Vanesko ,  Randall Paul Meyer ,  Patrick Alan Estep ,  Bashar Romanous

IPC: G06F8/41

CPC classification number: G06F8/453 ,  G06F8/433 ,  G06F8/451 ,  G06F8/457 ,  G06F8/458

Abstract: An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

公开(公告)号：US20230305848A1

公开(公告)日：2023-09-28

申请号：US17705112

申请日：2022-03-25

Applicant: Micron Technology, Inc.

Inventor： Allan Kennedy Porterfield ,  Skyler Arron Windh ,  Bashar Romanous

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F9/30043

Abstract: Schedule instructions of a program for execution on a coarse grained reconfigurable array having a plurality of tiles operable in parallel. The program identifies data flows through memory locations represented by memory variables and identifies instructions configured to transform data in the data flows. Based on a hardware profile identifying features of the coarse grained reconfigurable array, a scheduler is configured to generate a memory map. The memory map identifies, for each respective memory variable in the program, one of the tiles that contains a memory location represented by the respective memory variable. Based on the memory map reducing possible choices for a brute force search, the scheduler assigns the instructions to the tiles for execution, and determines timing of execution of the instructions in the tiles.