公开(公告)号：US09059115B2

公开(公告)日：2015-06-16

申请号：US14097003

申请日：2013-12-04

Applicant: Micron Technology, Inc.

Inventor： David A. Kewley ,  Brian Cleereman ,  Stephen W. Russell ,  Rex Stone ,  Anthony C. Krauth

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L21/32133 ,  H01L21/0337 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Abstract translation: 一些实施例包括形成存储器的方法。 可以在栅极堆叠上形成一系列光致抗蚀剂特征，并且可以在所述串联的末端形成占位符。 占位符可以通过间隙与所述系列的端部间隔开。 可以在光致抗蚀剂特征之上和之间在占位符上方以及在所述间隙内形成层。 该层可以沿光致抗蚀剂特征的边缘各向异性地蚀刻成多个第一垂直结构，并且沿着占位符的边缘进入第二垂直结构。 可以在第二垂直结构上形成掩模。 随后，可以使用第一垂直结构来模拟串门，同时使用掩模来对选择门进行图案化。 一些实施例包括形成导电流道的方法，并且一些实施例可以包括半导体结构。

公开(公告)号：US20140087558A1

公开(公告)日：2014-03-27

申请号：US14097003

申请日：2013-12-04

Applicant: Micron Technology, Inc.

Inventor： David A. Kewley ,  Brian Cleereman ,  Stephen W. Russell ,  Rex Stone ,  Anthony C. Krauth

IPC: H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/32133 ,  H01L21/0337 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Abstract translation: 一些实施例包括形成存储器的方法。 可以在栅极堆叠上形成一系列光致抗蚀剂特征，并且可以在所述串联的末端形成占位符。 占位符可以通过间隙与所述系列的端部间隔开。 可以在光致抗蚀剂特征之上和之间在占位符上方以及在所述间隙内形成层。 该层可以沿光致抗蚀剂特征的边缘各向异性地蚀刻成多个第一垂直结构，并且沿着占位符的边缘进入第二垂直结构。 可以在第二垂直结构上形成掩模。 随后，可以使用第一垂直结构来模拟串门，同时使用掩模来对选择门进行图案化。 一些实施例包括形成导电流道的方法，并且一些实施例可以包括半导体结构。