公开(公告)号：US20180175145A1

公开(公告)日：2018-06-21

申请号：US15895882

申请日：2018-02-13

Applicant: Micron Technology , Inc.

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/764 ,  H01L27/115

CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/78

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

公开(公告)号：US09929233B2

公开(公告)日：2018-03-27

申请号：US15385783

申请日：2016-12-20

Applicant: Micron Technology, Inc.

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L29/76 ,  H01L29/06 ,  H01L27/115 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/78

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

公开(公告)号：US09754879B2

公开(公告)日：2017-09-05

申请号：US14992280

申请日：2016-01-11

Applicant: Micron Technology, Inc.

Inventor： Zailong Bian

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating integrated circuitry includes forming a first conductive line. First elemental tungsten is deposited directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material. Dielectric material is formed elevationally over the first conductive line and a via is formed there-through to conductive material of the first conductive line at a location where the first tungsten was deposited. Second elemental tungsten is non-selectively deposited to within the via and electrically couples to the first conductive line. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via.

公开(公告)号：US09362495B2

公开(公告)日：2016-06-07

申请号：US14083069

申请日：2013-11-18

Applicant: Micron Technology, Inc.

Inventor： Zailong Bian

IPC: H01L29/04 ,  H01L47/00 ,  H01L45/00 ,  H01C1/02 ,  H01C7/13 ,  H01C17/06

CPC classification number: H01L45/1253 ,  H01C1/02 ,  H01C7/13 ,  H01C17/06 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683 ,  Y10T29/49099

Abstract: Methods, devices, and systems associated with resistance variable memory device structures can include a method of forming a confined resistance variable memory cell structure includes forming a resistance variable material such that a first unmodified portion of the resistance variable material contacts a bottom electrode and a second unmodified portion of the resistance variable material contacts a top electrode.

Abstract translation: 与电阻可变存储器件结构相关联的方法，器件和系统可以包括形成受限电阻可变存储单元结构的方法，包括形成电阻可变材料，使得电阻可变材料的第一未修改部分接触底电极，第二 电阻可变材料的未改性部分接触顶部电极。

公开(公告)号：US20190096994A1

公开(公告)日：2019-03-28

申请号：US16200593

申请日：2018-11-26

Applicant: Micron Technology, Inc.

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L29/06 ,  H01L21/764 ,  H01L27/105 ,  H01L21/762 ,  H01L27/11521 ,  H01L27/115 ,  H01L29/78

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

公开(公告)号：US20140151629A1

公开(公告)日：2014-06-05

申请号：US14083069

申请日：2013-11-18

Applicant: Micron Technology, Inc.

Inventor： Zailong Bian

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01C1/02 ,  H01C7/13 ,  H01C17/06 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683 ,  Y10T29/49099

Abstract: Methods, devices, and systems associated with resistance variable memory device structures are described herein. In one or more embodiments, a method of forming a confined resistance variable memory cell structure includes forming a resistance variable material such that a first unmodified portion of the resistance variable material contacts a bottom electrode and a second unmodified portion of the resistance variable material contacts a top electrode.

Abstract translation: 本文描述了与电阻可变存储器件结构相关联的方法，器件和系统。 在一个或多个实施例中，形成限制电阻可变存储单元结构的方法包括形成电阻可变材料，使得电阻可变材料的第一未修改部分接触底电极，并且电阻可变材料的第二未修改部分接触 顶部电极。

公开(公告)号：US11626481B2

公开(公告)日：2023-04-11

申请号：US17498468

申请日：2021-10-11

Applicant: Micron Technology, Inc.

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L29/06 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/105 ,  H01L21/762 ,  H01L27/115 ,  H01L29/78

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

公开(公告)号：US11171205B2

公开(公告)日：2021-11-09

申请号：US16813514

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L29/06 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/105 ,  H01L21/762 ,  H01L27/115 ,  H01L29/78

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

公开(公告)号：US20200212175A1

公开(公告)日：2020-07-02

申请号：US16813514

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L29/06 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/105 ,  H01L21/762 ,  H01L27/115

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

公开(公告)号：US10170545B2

公开(公告)日：2019-01-01

申请号：US15895882

申请日：2018-02-13

Applicant: Micron Technology, Inc.

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L29/76 ,  H01L29/06 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/105 ,  H01L21/762 ,  H01L27/115 ,  H01L29/78

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.