公开(公告)号：US07853920B2

公开(公告)日：2010-12-14

申请号：US11437594

申请日：2006-05-19

申请人： Moshe E. Preil ,  Jun Ye ,  James N. Wiley ,  Shauh-Teh Juang ,  Michael J. Gassner

发明人： Moshe E. Preil ,  Jun Ye ,  James N. Wiley ,  Shauh-Teh Juang ,  Michael J. Gassner

IPC分类号： G06F17/50 ,  G06K9/00

CPC分类号： G03F7/7085 ,  G01N2021/95676 ,  G03F1/84 ,  G03F7/7065 ,  G03F7/70666

摘要： One embodiment of a method for detecting, sampling, analyzing, and correcting hot spots in an integrated circuit design allows the identification of the weakest patterns within each design layer, the accurate determination of the impact of process drifts upon the patterning performance of the real mask in a real scanner, and the optimum process correction, process monitoring, and RET improvements to optimize integrated circuit device performance and yield. The combination of high speed simulation coupled with massive data collection capability on actual aerial images and/or resist images at the specific patterns of interest provides a complete methodology for optimum RET implementation and process monitoring.

摘要翻译： 用于在集成电路设计中检测，采样，分析和校正热点的方法的一个实施例允许识别每个设计层内的最弱图案，精确确定工艺的影响漂移对真实掩模的图案化性能 在真正的扫描仪中，以及最佳的过程校正，过程监控和RET改进，以优化集成电路器件的性能和产量。 将高速仿真与实际航空图像上的海量数据收集能力和/或特定感兴趣图像的抗蚀图像相结合，为最佳的RET实施和过程监控提供了一个完整的方法。

公开(公告)号：US20120021343A1

公开(公告)日：2012-01-26

申请号：US13244218

申请日：2011-09-23

申请人： Jun Ye ,  Moshe E. Preil ,  Xun Chen ,  Shauh-Teh Juang ,  James Wiley

发明人： Jun Ye ,  Moshe E. Preil ,  Xun Chen ,  Shauh-Teh Juang ,  James Wiley

IPC分类号： G03F1/00

CPC分类号： G03F7/70641 ,  G03F1/44 ,  G03F7/705 ,  G03F7/70625

摘要： A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.

摘要翻译： 公开了一种用于识别掩模的设备区域中的处理窗口签名图案的方法。 签名图案集合地提供了对一组工艺条件参数对光刻工艺的变化的唯一响应。 签名模式可以监控相关的过程状态参数，以了解过程漂移的迹象，分析过程状态参数，以确定哪些是限制和影响芯片产量，分析过程状态参数的变化以确定应反馈的校正 进入光刻工艺或转发到蚀刻工艺，识别不按照预期将预期图案转印到晶片的特定掩模，以及鉴定相对于工艺条件参数的变化共享共同特性并以类似方式表现的掩模组， 将图案转移到晶片。

公开(公告)号：US20100151364A1

公开(公告)日：2010-06-17

申请号：US12660313

申请日：2010-02-23

申请人： Jun Ye ,  Moshe E. Preil ,  Xun Chen ,  Shauh-Teh Juang ,  James Wiley

发明人： Jun Ye ,  Moshe E. Preil ,  Xun Chen ,  Shauh-Teh Juang ,  James Wiley

IPC分类号： G03F1/00

CPC分类号： G03F7/70641 ,  G03F1/44 ,  G03F7/705 ,  G03F7/70625

摘要： A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.

公开(公告)号：US07695876B2

公开(公告)日：2010-04-13

申请号：US11466978

申请日：2006-08-24

申请人： Jun Ye ,  Moshe E. Preil ,  Xun Chen ,  Shauh-Teh Juang ,  James Wiley

发明人： Jun Ye ,  Moshe E. Preil ,  Xun Chen ,  Shauh-Teh Juang ,  James Wiley

IPC分类号： G03F9/00 ,  G03C5/00

CPC分类号： G03F7/70641 ,  G03F1/44 ,  G03F7/705 ,  G03F7/70625

摘要： A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.

摘要翻译： 公开了一种用于识别掩模的设备区域中的处理窗口签名图案的方法。 签名图案集合地提供了对一组工艺条件参数对光刻工艺的变化的唯一响应。 签名模式可以监控相关的过程状态参数，以了解过程漂移的迹象，分析过程状态参数，以确定哪些是限制和影响芯片产量，分析过程状态参数的变化以确定应反馈的校正 进入光刻过程或转发到蚀刻工艺，识别不按照预期将预期图案转印到晶片的特定掩模，以及鉴定相对于工艺条件参数的变化共享共同特性并以类似方式表现的掩模组， 将图案转移到晶片。

公开(公告)号：US08318391B2

公开(公告)日：2012-11-27

申请号：US13244218

申请日：2011-09-23

申请人： Jun Ye ,  Moshe E. Preil ,  Xun Chen ,  Shauh-Teh Juang ,  James Wiley

发明人： Jun Ye ,  Moshe E. Preil ,  Xun Chen ,  Shauh-Teh Juang ,  James Wiley

IPC分类号： G03F9/00 ,  G03C5/00

CPC分类号： G03F7/70641 ,  G03F1/44 ,  G03F7/705 ,  G03F7/70625

摘要： A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.

摘要翻译： 公开了一种用于识别掩模的设备区域中的处理窗口签名图案的方法。 签名图案集合地提供了对一组工艺条件参数对光刻工艺的变化的唯一响应。 签名模式可以监控相关的过程状态参数，以了解过程漂移的迹象，分析过程状态参数，以确定哪些是限制和影响芯片产量，分析过程状态参数的变化以确定应反馈的校正 进入光刻过程或转发到蚀刻工艺，识别不按照预期将预期图案转印到晶片的特定掩模，以及鉴定相对于工艺条件参数的变化共享共同特性并以类似方式表现的掩模组， 将图案转移到晶片。

公开(公告)号：US08057967B2

公开(公告)日：2011-11-15

申请号：US12660313

申请日：2010-02-23

申请人： Jun Ye ,  Moshe E. Preil ,  Xun Chen ,  Shauh-Teh Juang ,  James Wiley

发明人： Jun Ye ,  Moshe E. Preil ,  Xun Chen ,  Shauh-Teh Juang ,  James Wiley

IPC分类号： G03F9/00

CPC分类号： G03F7/70641 ,  G03F1/44 ,  G03F7/705 ,  G03F7/70625

摘要： A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.

摘要翻译： 公开了一种用于识别掩模的设备区域中的处理窗口签名图案的方法。 签名图案集合地提供了对一组工艺条件参数对光刻工艺的变化的唯一响应。 签名模式可以监控相关的过程状态参数，以了解过程漂移的迹象，分析过程状态参数，以确定哪些是限制和影响芯片产量，分析过程状态参数的变化以确定应反馈的校正 进入光刻过程或转发到蚀刻工艺，识别不按照预期将预期图案转印到晶片的特定掩模，以及鉴定相对于工艺条件参数的变化共享共同特性并以类似方式表现的掩模组， 将图案转移到晶片。

公开(公告)号：US06516085B1

公开(公告)日：2003-02-04

申请号：US09304437

申请日：1999-05-03

申请人： James N. Wiley ,  Jun Ye ,  Shauh-Teh Juang ,  David S. Alles ,  Yen-Wen Lu ,  Yu Cao

发明人： James N. Wiley ,  Jun Ye ,  Shauh-Teh Juang ,  David S. Alles ,  Yen-Wen Lu ,  Yu Cao

IPC分类号： G06K900

CPC分类号： G06T7/001 ,  G06T2207/30148

摘要： Disclosed is a method of inspecting a reticle defining a circuit layer pattern that is used within a corresponding semiconductor process to generate corresponding patterns on a semiconductor wafer. A test image of the reticle is provided, and the test image has a plurality of test characteristic values. A baseline image containing an expected pattern of the test image is also provided. The baseline image has a plurality of baseline characteristic values that correspond to the test characteristic values. The test characteristic values are compared to the baseline characteristic values such that a plurality of difference values are calculated for each pair of test and baseline characteristic values. Statistical information is also collected.

摘要翻译： 公开了一种检查限定在相应半导体工艺中使用的电路层图案的掩模版的方法，以在半导体晶片上产生相应的图案。 提供了掩模版的测试图像，并且测试图像具有多个测试特性值。 还提供了包含测试图像的预期图案的基线图像。 基线图像具有对应于测试特征值的多个基线特征值。 将测试特征值与基线特征值进行比较，使得针对每对测试和基线特征值计算多个差值。 还收集统计资料。

公开(公告)号：US06529621B1

公开(公告)日：2003-03-04

申请号：US09213744

申请日：1998-12-17

申请人： Lance A. Glasser ,  Jun Ye ,  Shauh-Teh Juang ,  David S. Alles ,  James N. Wiley

发明人： Lance A. Glasser ,  Jun Ye ,  Shauh-Teh Juang ,  David S. Alles ,  James N. Wiley

IPC分类号： G06K900

CPC分类号： G03F1/84

摘要： A reusable circuit design for use with electronic design automation EDA tools in designing integrated circuits is disclosed, as well as reticle inspection and fabrication methods that are based on such reusable circuit design. The reusable circuit design is stored on a computer readable medium and contains an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit. The layout pattern includes a flagged critical region which corresponds to a critical region on a reticle or integrated circuit that is susceptible to special inspection or fabrication procedures. In one aspect of the reusable circuit design, the special analysis is performed during one from a group consisting of reticle inspection, reticle production, integrated circuit fabrication, and fabricated integrated circuit inspection.

公开(公告)号：US06748103B2

公开(公告)日：2004-06-08

申请号：US10359444

申请日：2003-02-04

申请人： Lance A. Glasser ,  Jun Ye ,  Shauh-Teh Juang ,  David S. Alles ,  James N. Wiley

发明人： Lance A. Glasser ,  Jun Ye ,  Shauh-Teh Juang ,  David S. Alles ,  James N. Wiley

IPC分类号： G06K900

CPC分类号： G03F1/84

摘要： A reusable circuit design for use with electronic design automation EDA tools in designing integrated circuits is disclosed, as well as reticle inspection and fabrication methods that are based on such reusable circuit design. The reusable circuit design is stored on a computer readable medium and contains an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit. The layout pattern includes a flagged critical region which corresponds to a critical region on a reticle or integrated circuit that is susceptible to special inspection or fabrication procedures. In one aspect of the reusable circuit design, the special analysis is performed during one from a group consisting of reticle inspection, reticle production, integrated circuit fabrication, and fabricated integrated circuit inspection.

摘要翻译： 公开了一种用于设计电子设计自动化EDA工具的可复用电路设计，以及基于这种可重复使用的电路设计的标线检查和制造方法。 可重复使用的电路设计存储在计算机可读介质上，并且包含用于集成电路上的至少一层电路设计的布局图案的电子表示。 布局图案包括标记的临界区域，其对应于易于进行特殊检查或制造程序的掩模版或集成电路上的临界区域。 在可重复使用的电路设计的一个方面，特别的分析是在一个由标线检查，标线制作，集成电路制造和制造的集成电路检查组成的组中进行的。

公开(公告)号：US06654489B2

公开(公告)日：2003-11-25

申请号：US10314030

申请日：2002-12-04

申请人： James N. Wiley ,  Jun Ye ,  Shauh-Teh Juang ,  David S. Alles ,  Yen-Wen Lu ,  Yu Cao

发明人： James N. Wiley ,  Jun Ye ,  Shauh-Teh Juang ,  David S. Alles ,  Yen-Wen Lu ,  Yu Cao

IPC分类号： G06K900

CPC分类号： G06T7/001 ,  G06T2207/30148

摘要： Disclosed is a method of inspecting a reticle defining a circuit layer pattern that is used within a corresponding semiconductor process to generate corresponding patterns on a semiconductor wafer. A test image of the reticle is provided, and the test image has a plurality of test characteristic values. A baseline image containing an expected pattern of the test image is also provided. The baseline image has a plurality of baseline characteristic values that correspond to the test characteristic values. The test characteristic values are compared to the baseline characteristic values such that a plurality of difference values are calculated for each pair of test and baseline characteristic values. Statistical information is also collected.