公开(公告)号：US20250119098A1

公开(公告)日：2025-04-10

申请号：US18891556

申请日：2024-09-20

Applicant: NXP B.V.

Inventor： Harish Eleendram ,  Anand Kumar Sinha ,  Ateet Omer ,  Siyaram Sahu ,  Vishwajit Babasaheb Bugade

IPC: H03B5/36

Abstract: A compensation system for a crystal oscillator including a DC level comparator, current compensation circuitry, and a compensation controller. The crystal oscillator includes an amplifier with a feedback resistance coupled between first and second terminals of a crystal resonator. The DC level comparator may be a hysteretic comparator that compares a DC level of the first node with a DC level of the second node and to provide a corresponding compensation signal. The compensation controller controls a magnitude and direction of the compensation current applied to the first node by the current compensation circuitry based on the compensation signal. The current compensation circuitry sources current to or sinks current from the first node until the leakage current is minimized. The compensation controller may include a digital counter the generates a digital control value used to activate selected current sources or sinks for developing the compensation current.

公开(公告)号：US20250119141A1

公开(公告)日：2025-04-10

申请号：US18883115

申请日：2024-09-12

Applicant: NXP B.V.

Inventor： Harish Eleendram ,  Anand Kumar Sinha

IPC: H03K19/00 ,  H03K3/012 ,  H03K3/037

Abstract: An inverter circuit, usable in a clock buffer circuit, includes a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to an input node and first current electrodes of the first and second transistors are coupled at an output node. The inverter circuit also includes a first set of additional transistors of the first conductivity type, a second set of additional transistors of the second conductivity type, and a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period.