公开(公告)号：US12164326B2

公开(公告)日：2024-12-10

申请号：US18168622

申请日：2023-02-14

Applicant: NXP B.V.

Inventor： Vishwajit Babasaheb Bugade ,  Anand Kumar Sinha ,  Krishna Thakur ,  Siyaram Sahu

IPC: H03K5/01 ,  G06F1/08 ,  H03K5/00

Abstract: A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit is provided. The delay circuit receives a reference clock signal and generates a phase shifted clock signal. A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.

公开(公告)号：US20250119098A1

公开(公告)日：2025-04-10

申请号：US18891556

申请日：2024-09-20

Applicant: NXP B.V.

Inventor： Harish Eleendram ,  Anand Kumar Sinha ,  Ateet Omer ,  Siyaram Sahu ,  Vishwajit Babasaheb Bugade

IPC: H03B5/36

Abstract: A compensation system for a crystal oscillator including a DC level comparator, current compensation circuitry, and a compensation controller. The crystal oscillator includes an amplifier with a feedback resistance coupled between first and second terminals of a crystal resonator. The DC level comparator may be a hysteretic comparator that compares a DC level of the first node with a DC level of the second node and to provide a corresponding compensation signal. The compensation controller controls a magnitude and direction of the compensation current applied to the first node by the current compensation circuitry based on the compensation signal. The current compensation circuitry sources current to or sinks current from the first node until the leakage current is minimized. The compensation controller may include a digital counter the generates a digital control value used to activate selected current sources or sinks for developing the compensation current.

公开(公告)号：US20250055446A1

公开(公告)日：2025-02-13

申请号：US18771327

申请日：2024-07-12

Applicant: NXP B.V.

Inventor： Vishwajit Babasaheb Bugade ,  Anand Kumar Sinha ,  Krishna Thakur ,  Siyaram Sahu

IPC: H03K3/017 ,  G06F1/08 ,  H03K5/00 ,  H03K5/01

Abstract: A method for quadrature phase shifted clock generation with duty cycle correction includes A reference clock is delayed with a delay circuit to generate a delayed clock, wherein a delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock comprise a plurality of states comprising a first state and a second state. A first edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. A second edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. The control value is driven to the first edge value during the second state of the delayed clock and to the second edge value during the first state of the delayed clock.

公开(公告)号：US20240192720A1

公开(公告)日：2024-06-13

申请号：US18168622

申请日：2023-02-14

Applicant: NXP B.V.

Inventor： Vishwajit Babasaheb Bugade ,  Anand Kumar Sinha ,  Krishna Thakur ,  Siyaram Sahu

IPC: G06F1/08 ,  H03K5/01

CPC classification number: G06F1/08 ,  H03K5/01 ,  H03K2005/00013

Abstract: A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit is provided. The delay circuit receives a reference clock signal and generates a phase shifted clock signal. A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.