公开(公告)号：US06393570B1

公开(公告)日：2002-05-21

申请号：US09322378

申请日：1999-05-28

申请人： Nathaniel Henderson ,  Eric Davis ,  Kirk Blattman ,  Glenn Connery

发明人： Nathaniel Henderson ,  Eric Davis ,  Kirk Blattman ,  Glenn Connery

IPC分类号： G06F132

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D50/20

摘要： Low power event monitoring enabling logic allows wake up devices to maintain their proper functionality in the event of a momentary power loss, or in the event the operating system does not properly load upon power-up. The technology is particularly suited for use with network interface card supporting Wake-On-LAN functions. A component with low power enabling logic is provided for a system having power management resources responsive to power management event signals to switch to an operating state. The component comprises power logic having a first mode in which power consumption is limited to a first specified level and a second mode in which power consumption is limited to a second specified level higher than the first specified level. The component includes an interface to nonvolatile memory storing a control signal. Logic is coupled to the interface to the nonvolatile memory and responsive to detection of a power supply voltage to read in the first mode the control signal from the nonvolatile memory, and to the signal the power logic to enter the second mode in response to a specified state of the control signal. Monitoring resources operating in the second mode monitor for an event, and in response to detection of the event produce a signal to cause the system switch to the operating mode.

摘要翻译： 低功率事件监控启用逻辑允许唤醒设备在瞬间掉电的情况下维护其正常功能，或者在上电时操作系统未正确加载的情况下。 该技术特别适用于支持LAN唤醒功能的网络接口卡。 提供具有低功率使能逻辑的组件，用于具有响应于电力管理事件信号以切换到操作状态的电力管理资源的系统。 该组件包括具有第一模式的功率逻辑，其中功率消耗被限制到第一指定电平，而第二模式将功耗限制在高于第一指定电平的第二指定电平。 该组件包括存储控制信号的非易失性存储器的接口。 逻辑耦合到与非易失性存储器的接口，并且响应于检测到电源电压，以第一模式读取来自非易失性存储器的控制信号，并响应于指定的功率逻辑进入第二模式的信号 状态的控制信号。 在事件的第二模式监视器中监视资源，并且响应于事件的检测产生信号以使系统切换到操作模式。

公开(公告)号：US06678728B1

公开(公告)日：2004-01-13

申请号：US09454783

申请日：1999-12-03

申请人： Krishna Uppunda ,  Eric Davis ,  Nathaniel Henderson ,  Chi-Lie Wang ,  Alexander Herrera

发明人： Krishna Uppunda ,  Eric Davis ,  Nathaniel Henderson ,  Chi-Lie Wang ,  Alexander Herrera

IPC分类号： G06F15177

CPC分类号： H04L12/12 ,  Y02D50/40

摘要： A method and apparatus for automatically loading device status information into a network device. One embodiment comprises an apparatus in a network device, wherein the network device enters a sleep state under particular conditions. In one embodiment, the apparatus is for communicating with other devices on the network and comprises control circuitry that controls communication between the network device and the other devices on the network. The apparatus further comprises a memory device that stores configuration data for the control circuitry, wherein at least a portion of the configuration data is loaded into the control circuitry upon initialization of the network device. The apparatus further comprises a buffer that stores keep-alive data that is transmitted to a plurality of the other devices in the network to refresh the presence of the network device in the network, wherein the keep-alive data is loaded into the buffer from the memory device upon initialization of the network device.

摘要翻译： 一种用于将设备状态信息自动加载到网络设备中的方法和装置。 一个实施例包括网络设备中的设备，其中网络设备在特定条件下进入睡眠状态。 在一个实施例中，该设备用于与网络上的其他设备进行通信，并且包括控制网络设备与网络上的其他设备之间的通信的控制电路。 该装置还包括存储器件，其存储用于控制电路的配置数据，其中当网络设备初始化时，配置数据的至少一部分被加载到控制电路中。 所述设备还包括缓冲器，其存储传送到网络中的多个其他设备的保持活动数据，以刷新网络中网络设备的存在，其中保持活动数据从 初始化网络设备时的存储设备。

公开(公告)号：US06640262B1

公开(公告)日：2003-10-28

申请号：US09467724

申请日：1999-12-20

申请人： Krishna Uppunda ,  Eric R. Davis ,  Nathaniel Henderson ,  Chi-Lie Wang ,  Alexander Herrera

发明人： Krishna Uppunda ,  Eric R. Davis ,  Nathaniel Henderson ,  Chi-Lie Wang ,  Alexander Herrera

IPC分类号： G06F15177

CPC分类号： G06F15/7867

摘要： A method and apparatus for automatically configuring a configurable integrated circuit. One embodiment comprises a method for automatically loading data including configuration data to a configurable integrated circuit upon initialization of a system in which the configurable integrated circuit is embedded. The method of one embodiment comprises storing a plurality of commands and a plurality of data elements in a non-volatile memory of the system. The method further comprises reading contents of an initial address in the non-volatile memory. If the initial address contains a command, depending upon a type of the command, the method comprises writing contents of a next address in the non-volatile memory to a register space of the configurable integrated circuit, to a configuration space of the configurable integrated circuit, or to a command space of the configurable integrated circuit.

摘要翻译： 一种用于自动配置可配置集成电路的方法和装置。 一个实施例包括在嵌入可配置集成电路的系统的初始化时自动将包括配置数据的数据加载到可配置集成电路的方法。 一个实施例的方法包括将多个命令和多个数据元素存储在系统的非易失性存储器中。 该方法还包括读取非易失性存储器中的初始地址的内容。 如果初始地址包含命令，则取决于命令的类型，该方法包括将非易失性存储器中的下一个地址的内容写入可配置集成电路的寄存器空间到可配置集成电路的配置空间 ，或可配置集成电路的命令空间。

公开(公告)号：US06324652B1

公开(公告)日：2001-11-27

申请号：US09232862

申请日：1999-01-15

申请人： Nathaniel Henderson ,  David Brown ,  Lai-Chin Lo ,  Ngo Ho

发明人： Nathaniel Henderson ,  David Brown ,  Lai-Chin Lo ,  Ngo Ho

IPC分类号： G06F104

CPC分类号： G06F1/08

摘要： An asynchronous switching circuit for multiple indeterminate bursting clocks. In one embodiment, the present invention recites a clock-switching circuit that provides a single unclipped and glitch-free clock signal at its output from among multiple clock inputs. The clock-switching circuit is comprised of a plurality of asynchronously-enabled clock circuits, a plurality of blocking circuits, a synchronizing clock, and a logic gate. Each of the plurality of blocking circuits has an input lead respectively coupled to one of the plurality of asynchronously-enabled clock circuits, each of the plurality of blocking circuits also has an output coupled to all of the plurality of asynchronously-enabled clock circuits except the one to which its input is coupled. The synchronizing clock is coupled to each of the plurality of blocking circuits while the logic gate is coupled to each of the plurality of asynchronously-enabled clock circuits.

摘要翻译： 用于多个不确定的突发时钟的异步切换电路。 在一个实施例中，本发明描述了一种时钟切换电路，其在多个时钟输入的输出端提供单个未切断和无毛刺的时钟信号。 时钟切换电路由多个异步使能时钟电路，多个阻塞电路，同步时钟和逻辑门组成。 多个阻塞电路中的每一个具有分别耦合到多个异步使能时钟电路中的一个的输入引线，多个阻塞电路中的每一个还具有耦合到所有多个异步使能的时钟电路的输出，除了 其输入耦合到其中。 同步时钟耦合到多个阻塞电路中的每一个，同时逻辑门耦合到多个异步使能的时钟电路中的每一个。