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    Enhancing Quality of Contact Lists for Direct Marketing Campaigns
    1.
    发明申请
    Enhancing Quality of Contact Lists for Direct Marketing Campaigns 审中-公开
    提高直接营销活动联系人名单的质量

    公开(公告)号：US20100305988A1

    公开(公告)日：2010-12-02

    申请号：US12471941

    申请日：2009-05-26

    申请人： Nishant AGARWAL ,  Rajesh Chopra ,  Sharat Rapur

    发明人： Nishant AGARWAL ,  Rajesh Chopra ,  Sharat Rapur

    IPC分类号： G06Q10/00 ,  G06F17/30 ,  G06Q30/00

    CPC分类号： G06Q10/06395 ,  G06Q30/02

    摘要： A method, system, and computer program product are used for enhancing quality of contact lists for direct marketing campaigns. An embodiment of the method includes receiving a contact list that includes a plurality of customer profiles, and performing at least one of a counts verification check, a criteria outlier check, a data values check, and an output file check on the contact list. The method performs the aforementioned checks based at least partially on one or more quality check (QC) parameters. Further, the method includes generating a QC report that includes error statistics pertaining to at least one of the aforementioned checks. The method further generates an exceptions report based on the QC report and the QC parameters, and modifies the QC parameters based on the exceptions report.

    摘要翻译： 方法，系统和计算机程序产品用于提高直接营销活动的联系人列表的质量。 该方法的实施例包括接收包括多个客户简档的联系人列表，并且在联系人列表上执行计数验证检查，标准异常检查，数据值检查和输出文件检查中的至少一个。 该方法至少部分地基于一个或多个质量检查（QC）参数执行上述检查。 此外，该方法包括生成包括与上述检查中的至少一个相关的错误统计的QC报告。 该方法还基于QC报告和QC参数生成异常报告，并根据异常报告修改QC参数。

    Programmable built-in self-test architecture
    3.
    发明授权
    Programmable built-in self-test architecture 失效
    可编程内置自检架构

    公开(公告)号：US08069385B1

    公开(公告)日：2011-11-29

    申请号：US12501995

    申请日：2009-07-13

    申请人： Rajesh Chopra

    发明人： Rajesh Chopra

    IPC分类号： G11C29/44 ,  G11C29/54

    CPC分类号： G11C29/16

    摘要： A PBIST architecture is described. A data path circuit is configured for bit-to-associated bit comparisons of expected result data read from a tile with the expected result data read from result memory. The data path circuit is configured to write a first type of failure indication to first failure memory responsive to a data 0 being read from the result memory and a data 1 being read from the tile for a bit-to-associated bit comparison failure. The data path circuit is further configured to write a second type of failure indication to second failure memory responsive to a data 1 being read from the result memory and a data 0 being read from the tile for the bit-to-associated bit comparison.

    摘要翻译： 描述了PBIST架构。 数据路径电路被配置用于从瓦片读取的预期结果数据与从结果存储器读取的预期结果数据进行比特到比特比较。 数据路径电路被配置为响应于从结果存储器读取的数据0以及从瓦片读取的数据1用于比特到关联比特比较失败，向第一故障存储器写入第一类型的故障指示。 数据路径电路还被配置为响应于从结果存储器读取的数据1和从片中读取用于比特到关联比特比较的数据0，将第二类型的故障指示写入第二故障存储器。

    Programmable Test Engine (PCDTE) For Emerging Memory Technologies
    5.
    发明申请
    Programmable Test Engine (PCDTE) For Emerging Memory Technologies 有权
    可编程测试引擎（PCDTE）用于新兴内存技术

    公开(公告)号：US20110209002A1

    公开(公告)日：2011-08-25

    申请号：US13030358

    申请日：2011-02-18

    申请人： Rajesh Chopra

    发明人： Rajesh Chopra

    IPC分类号： G06F11/267

    CPC分类号： G06F11/263 ,  G06F11/27 ,  G11C29/56 ,  G11C29/56004

    摘要： A programmable characterization-debug-test engine (PCDTE) on an integrated circuit chip. The PCDTE includes an instruction memory that receives and stores instructions provided on a chip interface, and a configuration memory that receives and stores configuration values provided on the chip interface. The PCDTE also includes a controller that configures a plurality of address counters and data registers in response to the configuration values. The controller also executes the instructions, wherein read/write addresses and write data are retrieved from the counters in response to the instructions. The retrieved read/write addresses and write data are used to access a memory under test. Multiple ports of the memory under test may be simultaneously accessed. Multiple instructions may be linked. The instructions may specify special counting functions within the counters and/or specify integrated (linked) counters. The PCDTE may transmit information off of the chip to exercise transmit/receive circuitry of the chip.

    摘要翻译： 集成电路芯片上的可编程特征调试测试引擎（PCDTE）。 PCDTE包括接收并存储提供在芯片接口上的指令的指令存储器，以及接收并存储在芯片接口上提供的配置值的配置存储器。 PCDTE还包括响应于配置值配置多个地址计数器和数据寄存器的控制器。 控制器还执行指令，其中响应于指令从计数器检索读/写地址和写数据。 检索到的读/写地址和写数据用于访问被测内存。 可以同时访问被测存储器的多个端口。 可以链接多个指令。 指令可以指定计数器内的特殊计数功能和/或指定集成（链接）计数器。 PCDTE可以从芯片传送信息来锻炼芯片的发射/接收电路。

    Microprocessor having improved memory management unit and cache memory
    7.
    发明授权
    Microprocessor having improved memory management unit and cache memory 失效

    公开(公告)号：US06591340B2

    公开(公告)日：2003-07-08

    申请号：US10166503

    申请日：2002-06-10

    申请人： Rajesh Chopra ,  Shinichi Yoshioka ,  Mark Debbage ,  David Shepherd

    发明人： Rajesh Chopra ,  Shinichi Yoshioka ,  Mark Debbage ,  David Shepherd

    IPC分类号： G06F1200

    CPC分类号： G06F9/383 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3802 ,  G06F12/0888 ,  G06F12/1063 ,  G06F12/126 ,  G06F12/145

    摘要： Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed. A memory access operation is initiated on a predetermined memory location based on logical address information and permission information associated with the memory access operation. The virtual cache memory is accessed and a determination may be made if there is a match between logical address information of the memory access operation and logical address information stored in the entries of the virtual cache. In the event of a match, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the virtual cache memory as to whether the memory access operation is permitted. If the memory access operation is not permitted by the permission information of the particular entry of the virtual cache memory, then the translation lookaside buffer may be accessed based on the logical address information of the particular entry of the virtual cache memory. If there is a match between the logical address information of the particular entry of the virtual cache memory and the logical address information of a particular entry of the translation lookaside buffer, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the translation lookaside buffer as to whether the memory access operation is permitted by the permission information of the particular entry of the translation lookaside buffer. If the memory access operation is permitted by the permission information of the particular entry of the translation lookaside buffer, then the permission information of the particular entry of the virtual cache memory may be updated based on the permission information of the particular entry of the translation lookaside buffer and the memory access operation may be completed.

    Microprocessor having improved memory management unit and cache memory
    8.
    发明授权
    Microprocessor having improved memory management unit and cache memory 失效

    公开(公告)号：US06412043B1

    公开(公告)日：2002-06-25

    申请号：US09410506

    申请日：1999-10-01

    申请人： Rajesh Chopra ,  Shinichi Yoshioka ,  Mark Debbage ,  David Shepherd

    发明人： Rajesh Chopra ,  Shinichi Yoshioka ,  Mark Debbage ,  David Shepherd

    IPC分类号： G06F1200

    CPC分类号： G06F9/383 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3802 ,  G06F12/0888 ,  G06F12/1063 ,  G06F12/126 ,  G06F12/145

    摘要： Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed. A memory access operation is initiated on a predetermined memory location based on logical address information and permission information associated with the memory access operation. The virtual cache memory is accessed and a determination may be made if there is a match between logical address information of the memory access operation and logical address information stored in the entries of the virtual cache. In the event of a match, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the virtual cache memory as to whether the memory access operation is permitted. If the memory access operation is not permitted by the permission information of the particular entry of the virtual cache memory, then the translation lookaside buffer may be accessed based on the logical address information of the particular entry of the virtual cache memory. If there is a match between the logical address information of the particular entry of the virtual cache memory and the logical address information of a particular entry of the translation lookaside buffer, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the translation lookaside buffer as to whether the memory access operation is permitted by the permission information of the particular entry of the translation lookaside buffer. If the memory access operation is permitted by the permission information of the particular entry of the translation lookaside buffer, then the permission information of the particular entry of the virtual cache memory may be updated based on the permission information of the particular entry of the translation lookaside buffer and the memory access operation may be completed.

    SUBSTITUTE REDUNDANT MEMORY
    9.
    发明申请
    SUBSTITUTE REDUNDANT MEMORY 审中-公开
    备用冗余内存

    公开(公告)号：US20140082453A1

    公开(公告)日：2014-03-20

    申请号：US14031031

    申请日：2013-09-18

    申请人： Dipak K. Sikdar ,  Rajesh Chopra

    发明人： Dipak K. Sikdar ,  Rajesh Chopra

    IPC分类号： G06F11/10

    CPC分类号： G06F11/108 ,  G06F11/106 ,  G06F11/2094 ,  G11C29/06 ,  G11C29/12 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/50 ,  G11C29/808

    摘要： An integrated circuit (IC) chip for transparent and in-service or production repair of single to multiple memory cell defects in a word during the datapath transit of the word between core memory to the interface of the IC via capturing an accurate bit from a word during a write access to a known defective memory address, and by substituting in a non-defective bit into the word during a read access from a known defective memory address. The IC includes: address matching circuit (CAM), a random access memory (RAM) of substitute memory cells containing accurate associated bit data and bit location in word of defect, and data selection circuitry (MUXs) coupled together.

    摘要翻译： 一种集成电路（IC）芯片，用于通过从一个字中捕获一个精确的位，在核心存储器到IC的接口之间的数据路径传输期间，一个字中的单个到多个存储单元缺陷的单个或多个存储单元缺陷的透明和在线或生产修复 在对已知的有缺陷的存储器地址进行写入访问期间，并且在从已知的有缺陷的存储器地址进行的读取访问期间通过将非有缺陷的位替换成该字。 IC包括：地址匹配电路（CAM），包含精确关联位数据的替代存储单元的随机存取存储器（RAM）和缺陷字中的位位置，以及耦合在一起的数据选择电路（MUX）。