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    Memory Testing Techniques
    2.
    发明公开
    Memory Testing Techniques 审中-公开

    公开(公告)号：US20240136006A1

    公开(公告)日：2024-04-25

    申请号：US18400738

    申请日：2023-12-29

    申请人： Arm Limited

    发明人： Andy Wangkun Chen ,  Yannis Jallamion-Grive ,  Cyrille Nicolas Dray

    IPC分类号： G11C29/42 ,  G06F11/10 ,  G06F11/27 ,  G11C29/00 ,  G11C29/02 ,  G11C29/34

    CPC分类号： G11C29/42 ,  G06F11/102 ,  G06F11/106 ,  G06F11/27 ,  G11C29/025 ,  G11C29/34 ,  G11C29/781 ,  G11C29/802 ,  G11C2029/1802

    摘要： Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

    PROACTIVE LOSS NOTIFICATION AND HANDLING IN DATA STORAGE DEVICES
    4.
    发明公开
    PROACTIVE LOSS NOTIFICATION AND HANDLING IN DATA STORAGE DEVICES 审中-公开

    公开(公告)号：US20230385148A1

    公开(公告)日：2023-11-30

    申请号：US17752771

    申请日：2022-05-24

    申请人： Western Digital Technologies, Inc.

    发明人： Bhavya Krishna ,  Ramanathan Muthiah

    IPC分类号： G06F11/10

    CPC分类号： G06F11/106

    摘要： Devices, systems, and methods with proactive data loss notification and handling. A data storage device includes a memory and a controller. The controller includes a processor and controller memory. The controller memory stores a set of instructions that, when executed by the processor, instruct the controller to: detect an uncorrectable error correction code (UECC) during an internal data movement process of the storage device memory, modify a metadata field associated with a logical block address corresponding to the UECC, inform a host device about the UECC, and determine whether data stored in at least one adjacent region to the logical block address is lost.

    SEMICONDUCTOR DEVICES
    7.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20180307559A1

    公开(公告)日：2018-10-25

    申请号：US15715474

    申请日：2017-09-26

    申请人： SK hynix Inc.

    发明人： Jae In LEE ,  Yong Mi KIM

    IPC分类号： G06F11/10 ,  G11C29/52

    CPC分类号： G06F11/1068 ,  G06F11/106 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0409

    摘要： A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.

    Reducing uncorrectable errors based on a history of correctable errors
    9.
    发明授权
    Reducing uncorrectable errors based on a history of correctable errors 有权

    公开(公告)号：US10055287B2

    公开(公告)日：2018-08-21

    申请号：US15810722

    申请日：2017-11-13

    申请人： International Business Machines Corporation

    发明人： Glenn D. Gilda ,  Patrick J. Meaney

    IPC分类号： G06F11/10 ,  G11C29/52 ,  G11C29/44 ,  G06F11/00

    CPC分类号： G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C29/44 ,  G11C29/52

    摘要： In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.