公开(公告)号：US09037928B2

公开(公告)日：2015-05-19

申请号：US13732783

申请日：2013-01-02

申请人： Bendik Kleveland ,  Dipak K Sikdar ,  Rajesh Chopra ,  Jay Patel

发明人： Bendik Kleveland ,  Dipak K Sikdar ,  Rajesh Chopra ,  Jay Patel

IPC分类号： G06F11/20 ,  G11C29/44 ,  G11C29/16 ,  G06F11/10 ,  G11C29/12 ,  G11C29/06 ,  G11C29/04

CPC分类号： G06F11/2094 ,  G06F11/106 ,  G11C29/06 ,  G11C29/12 ,  G11C29/16 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/50 ,  G11C29/808 ,  G11C2029/0409

摘要： A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.

摘要翻译： 具有背景内置自检（BBIST）的存储器件包括多个存储器块; 一个用于临时从多个存储块中的一个存储器块中的一个卸载数据的存储器缓冲器; 以及存储器块应力控制器，用于当数据被暂时地卸载到存储器缓冲器上时，控制施加到存储器块之一的压力测试。 压力测试测试多个存储器块中的一个存储器块中的错误。

公开(公告)号：US20130173970A1

公开(公告)日：2013-07-04

申请号：US13732783

申请日：2013-01-02

申请人： Bendik Kleveland ,  Dipak K. Sikdar ,  Rajesh Chopra ,  Jay Patel

发明人： Bendik Kleveland ,  Dipak K. Sikdar ,  Rajesh Chopra ,  Jay Patel

IPC分类号： G11C29/44

CPC分类号： G06F11/2094 ,  G06F11/106 ,  G11C29/06 ,  G11C29/12 ,  G11C29/16 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/50 ,  G11C29/808 ,  G11C2029/0409

摘要： A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.

摘要翻译： 具有背景内置自检（BBIST）的存储器件包括多个存储器块; 一个用于临时从多个存储块中的一个存储器块中的一个卸载数据的存储器缓冲器; 以及存储器块应力控制器，用于当数据被暂时地卸载到存储器缓冲器上时，控制施加到存储器块之一的压力测试。 压力测试测试多个存储器块中的一个存储器块中的错误。

公开(公告)号：US07759916B2

公开(公告)日：2010-07-20

申请号：US12118773

申请日：2008-05-12

申请人： Bendik Kleveland

发明人： Bendik Kleveland

IPC分类号： G05F1/00 ,  G06F1/00

CPC分类号： G05F1/563 ,  H02M3/1584 ,  H02M2001/0032 ,  H02M2001/0045 ,  Y02B70/16

摘要： A voltage regulator device and accompanying methods are provided for providing efficient voltage regulation to an electronic device. Efficient regulator 400 receives an input voltage on VIN from a battery or some other power supply at node VIN and supplies a stable regulated voltage to load device 404 at node VOUT. Load device 404 pulls different amounts of current and requires different degrees of tolerance on the voltage at VOUT depending upon its operating conditions. Data collection and control circuit 401 is capable of enabling and disabling regulator 402 and regulator 403. Data collection and control circuit 401 is also capable of measuring certain performance parameters associated with load device 404 and the operating conditions of load device 404. Data collection and control circuit 401 enables regulator 402 if said operating conditions are such that when data collection and control circuit 401 enables regulator 403 the performance parameters associated with load 404 are below a predefined standard.

摘要翻译： 提供了一种电压调节器装置和相关方法，用于向电子设备提供有效的电压调节。 高效调节器400从节点VIN处的电池或其他电源接收VIN上的输入电压，并在节点VOUT向负载装置404提供稳定的调节电压。 负载装置404拉动不同数量的电流，并且根据其工作条件对VOUT上的电压需要不同程度的容差。 数据收集和控制电路401能够启用和禁用调节器402和调节器403.数据收集和控制电路401还能够测量与负载设备404相关联的某些性能参数和负载设备404的操作条件。数据收集和控制 如果所述操作条件使得当数据收集和控制电路401启用调节器403时，与加载404相关联的性能参数低于预定标准，则电路401使得调节器402能够启用调节器402。

公开(公告)号：US07564707B2

公开(公告)日：2009-07-21

申请号：US11843404

申请日：2007-08-22

申请人： Bendik Kleveland

发明人： Bendik Kleveland

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  H01L27/101 ,  H01L27/112 ,  H01L27/1122

摘要： An apparatus includes a semiconductor substrate, elongated diffused well regions, and elongated conductors. The semiconductor substrate has a first electrical conductivity type. The elongated diffused well regions are in the semiconductor substrate. The diffused well regions have a second electrical conductivity type opposite the first electrical conductivity type. Each of the elongated electrical conductors crosses the diffused well regions at respective locations of one-time programmable memory cells. Each of the memory cells includes a antifuse structure between the respective diffused well region and the respective electrical conductor. Each of the memory cells has a first state in which the antifuse structure has a first electrical resistance and a second state in which the antifuse structure has a second electrical resistance lower than the first electrical resistance. In the second state, each of the memory cells includes a rectifying junction between the respective diffused well region and the respective electrical conductor.

摘要翻译： 一种装置包括半导体衬底，细长扩散阱区和细长导体。 半导体衬底具有第一导电类型。 细长扩散阱区位于半导体衬底中。 扩散阱区具有与第一导电类型相反的第二导电类型。 每个细长电导体在一次可编程存储器单元的相应位置处与扩散阱区域交叉。 每个存储单元包括在各个扩散阱区域和相应的电导体之间的反熔丝结构。 每个存储单元具有其中反熔丝结构具有第一电阻的第一状态和其中反熔丝结构具有低于第一电阻的第二电阻的第二状态。 在第二状态下，每个存储单元包括各个扩散阱区和相应电导体之间的整流结。

公开(公告)号：US20080278247A1

公开(公告)日：2008-11-13

申请号：US12171277

申请日：2008-07-10

申请人： Stanley Wang ,  Bendik Kleveland ,  Thomas H. Lee

发明人： Stanley Wang ,  Bendik Kleveland ,  Thomas H. Lee

IPC分类号： H03B1/04

CPC分类号： H03L7/099

摘要： A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).

公开(公告)号：US20060291303A1

公开(公告)日：2006-12-28

申请号：US11158396

申请日：2005-06-22

申请人： Bendik Kleveland ,  Tae Lee ,  Seung Yu ,  Chia Yang ,  Feng Li ,  Xiaoyu Yang

发明人： Bendik Kleveland ,  Tae Lee ,  Seung Yu ,  Chia Yang ,  Feng Li ,  Xiaoyu Yang

IPC分类号： G11C29/00

CPC分类号： G11C29/816 ,  G11C17/14

摘要： A method and apparatus for programming a memory array are disclosed. In one embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, the word line is repaired with a redundant word line. The word lines are then reprogrammed and rechecked for defects. In another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, that word line is repaired along with a previously-programmed adjacent word line. In yet another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line and a previously-programmed adjacent word line. If a defect is detected on that word line, that word line and the previously-programmed adjacent word line are repaired with redundant word lines.

摘要翻译： 公开了一种用于对存储器阵列进行编程的方法和装置。 在一个实施例中，在每个字线被编程之后，尝试检测该字线上的缺陷。 如果检测到缺陷，则用冗余字线修复字线。 字线然后被重新编程并重新检查缺陷。 在另一个实施例中，在每个字线被编程之后，尝试检测该字线上的缺陷。 如果检测到缺陷，则该字线与预先编程的相邻字线一起被修复。 在另一个实施例中，在每个字线被编程之后，尝试检测该字线上的缺陷和预先编程的相邻字线。 如果在该字线上检测到缺陷，则该字线和先前编程的相邻字线用冗余字线修复。

公开(公告)号：US06816410B2

公开(公告)日：2004-11-09

申请号：US10809146

申请日：2004-03-25

申请人： Bendik Kleveland ,  Roy E. Scheuerlein

发明人： Bendik Kleveland ,  Roy E. Scheuerlein

IPC分类号： G11C1604

CPC分类号： B82Y10/00 ,  G11C5/025 ,  G11C7/062 ,  G11C7/067 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0028 ,  G11C17/16 ,  G11C17/165 ,  G11C17/18 ,  G11C2207/063 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/0688 ,  H01L27/1021

摘要： A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.

公开(公告)号：US06567304B1

公开(公告)日：2003-05-20

申请号：US10144451

申请日：2002-05-09

申请人： Bendik Kleveland

发明人： Bendik Kleveland

IPC分类号： G11C1604

CPC分类号： G11C11/5642 ,  G11C11/56 ,  G11C11/5628 ,  G11C16/349

摘要： The preferred embodiments described herein provide a memory device and method for reliably reading multi-bit data from a write-many memory cell. In one preferred embodiment, a non-volatile, write-many memory cell operative to store multiple bits is provided, and the number of program/erase cycles to the write-many memory cell is limited. Limiting the number of program/erase cycles increases the probability that multi-bit data will be correctly read from the memory cell. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

摘要翻译： 本文描述的优选实施例提供了一种用于从多写存储器单元可靠地读取多位数据的存储器件和方法。 在一个优选实施例中，提供了可操作以存储多个位的非易失性，多写入存储器单元，并且限制写入许多存储器单元的编程/擦除周期数。 限制编程/擦除周期的数量增加了从存储器单元正确读取多位数据的概率。 提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

公开(公告)号：US06515904B2

公开(公告)日：2003-02-04

申请号：US09895960

申请日：2001-06-29

申请人： Christopher S. Moore ,  Bendik Kleveland ,  Roger W. March ,  James M. Cleeves ,  Roy E. Scheuerlein

发明人： Christopher S. Moore ,  Bendik Kleveland ,  Roger W. March ,  James M. Cleeves ,  Roy E. Scheuerlein

IPC分类号： G11C1600

CPC分类号： G11C8/08 ,  G11C7/062 ,  G11C7/067 ,  G11C7/18 ,  G11C16/10 ,  G11C2207/063

摘要： The preferred embodiments described herein provide a method and system for increasing programming bandwidth in a non-volatile memory device. In one preferred embodiment, a memory device is provided with a plurality of bits to be stored in a respective plurality of memory cells along a wordline. Some of the bits represent a programmed state, and others represent an un-programmed state. The duration of the programming pulse applied to the wordline is determined by the number of bits that represent the programmed state. In another preferred embodiment, the plurality of bits to be stored in the memory device comprises a first set of bits representing a modification to the stored data and a second set of bits representing an un-programmed state. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

公开(公告)号：US06486728B2

公开(公告)日：2002-11-26

申请号：US09809878

申请日：2001-03-16

申请人： Bendik Kleveland

发明人： Bendik Kleveland

IPC分类号： G05F302

CPC分类号： H02M3/073 ,  H02M2001/0041

摘要： An integrated voltage source includes a charge pump having multiple charge pump stages connected in series. A first one of the these charge pump stages is connected to the high voltage output of the charge pump, and the remaining charge pump stages are coupled to this first charge pump stage in a manner such that substantially all the charge pumped by all of the additional charge pump stages is also pumped by the first charge pump stage. In one mode of operation, the first charge pump stage and at least one additional charge pump stage are enabled. In another mode of operation, the first charge pump stage and at least two additional charge pump stages are enabled. A control circuit determines the mode of operation and, therefore, the number of charge pump stages that are enabled.

摘要翻译： 集成电压源包括具有串联连接的多个电荷泵级的电荷泵。 这些电荷泵级中的第一级连接到电荷泵的高电压输出，并且剩余的电荷泵级以这样的方式耦合到该第一电荷泵级，使得基本上所有的电荷被所有额外的 电荷泵级也由第一电荷泵级泵送。 在一种操作模式中，启用第一电荷泵级和至少一个额外的电荷泵级。 在另一种操作模式中，启用第一电荷泵级和至少两个额外的电荷泵级。 控制电路确定操作模式，因此确定启用的电荷泵级数。