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公开(公告)号:US20240404966A1
公开(公告)日:2024-12-05
申请号:US18801005
申请日:2024-08-12
Applicant: Oracle International Corporation
Inventor: Michael Henry Soltau Dayringer , Anatoly Yakovlev , Ji Eun Jang , Hesam Fathi Moghadam , David Hopkins
Abstract: Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system.
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2.
公开(公告)号:US20200342265A1
公开(公告)日:2020-10-29
申请号:US16718164
申请日:2019-12-17
Applicant: Oracle International Corporation
Inventor: Jingxiao Cai , Sandeep Agrawal , Sam Idicula , Venkatanathan Varadarajan , Anatoly Yakovlev , Nipun Agarwal
Abstract: According to an embodiment, a method includes generating a first dataset sample from a dataset, calculating a first validation score for the first dataset sample and a machine learning model, and determining whether a difference in validation score between the first validation score and a second validation score satisfies a first criteria. If the difference in validation score does not satisfy the first criteria, the method includes generating a second dataset sample from the dataset. If the difference in validation score does satisfy the first criteria, the method includes updating a convergence value and determining whether the updated convergence value satisfies a second criteria. If the updated convergence value satisfies the second criteria, the method includes returning the first dataset sample. If the updated convergence value does not satisfy the second criteria, the method includes generating the second dataset sample from the dataset.
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3.
公开(公告)号:US20200334569A1
公开(公告)日:2020-10-22
申请号:US16388830
申请日:2019-04-18
Applicant: Oracle International Corporation
Inventor: Hesam Fathi Moghadam , Sandeep Agrawal , Venkatanathan Varadarajan , Anatoly Yakovlev , Sam Idicula , Nipun Agarwal
Abstract: Techniques are provided for selection of machine learning algorithms based on performance predictions by using hyperparameter predictors. In an embodiment, for each mini-machine learning model (MML model) of a plurality of MML models, a respective hyperparameter predictor set that predicts a respective set of hyperparameter settings for a first data set is trained. Each MML model represents a respective reference machine learning model (RML model) of a plurality of RML models. A first plurality of data set samples is generated from the first data set. A first plurality of first meta-feature sets is generated, each first meta-feature set describing a respective first data set sample of said first plurality. A respective target set of hyperparameter settings are generated for said each MML model using a hypertuning algorithm. The first plurality of first meta-feature sets and the respective target set of hyperparameter settings are used to train the respective hyperparameter predictor set. Each hyperparameter predictor set is used during training and inference to improve the accuracy of automatically selecting a RML model per data set.
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公开(公告)号:US12094841B2
公开(公告)日:2024-09-17
申请号:US17306870
申请日:2021-05-03
Applicant: Oracle International Corporation
Inventor: Michael Henry Soltau Dayringer , Anatoly Yakovlev , Ji Eun Jang , Hesam Fathi Moghadam , David Hopkins
CPC classification number: H01L23/645 , G05F1/462 , H01L23/5227 , H01L24/17 , H02M1/14 , H02M3/158 , H01F27/24 , H01L2924/1206 , H02M1/0048
Abstract: Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system.
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公开(公告)号:US20240281455A1
公开(公告)日:2024-08-22
申请号:US18444454
申请日:2024-02-16
Applicant: Oracle International Corporation
Inventor: Youssef Mohamed Saied , Mohamed Ridha Chahed , Anatoly Yakovlev , Sandeep R. Agrawal , Sanjay Jinturkar , Nipun Agarwal
CPC classification number: G06F16/285 , G06F16/2282
Abstract: Disclosed is an improved approach to implement anomaly detection, where an ensemble detection mechanism is provided. An improvement is provided for the KNN algorithm where scaling is applied to permit efficient detection of multiple categories of anomalies. Further extensions are used to optimize local anomaly detection.
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公开(公告)号:US10983944B2
公开(公告)日:2021-04-20
申请号:US16251066
申请日:2019-01-17
Applicant: Oracle International Corporation
Inventor: Navaneeth P. Jamadagni , Ji Eun Jang , Anatoly Yakovlev , Vincent Lee , Guanghua Shu , Mark Semmelmeyer
Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.
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公开(公告)号:US20250094777A1
公开(公告)日:2025-03-20
申请号:US18821539
申请日:2024-08-30
Applicant: Oracle International Corporation
Inventor: Anatoly Yakovlev , Sandeep R. Agrawal , Karoon Rashedi Nia , Ridha Chahed , Sanjay Jinturkar , Nipun Agarwal
IPC: G06N3/0455
Abstract: The present disclosure relates to LLM orchestration with vector store generation. An embeddings model may be selected to generate an embedding for a digital artifact. Metadata for the digital artifact may also be generated and stored in a vector store in association with the embedding. A user query may be received and categorized. One of a plurality of machine learning models may be selected based on the categorization of the user query. A prompt may be generated based at least in part on the user query, and the selected machine learning model may generate a response to the user query based at least in part on the prompt.
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公开(公告)号:US20240086763A1
公开(公告)日:2024-03-14
申请号:US17944949
申请日:2022-09-14
Applicant: Oracle International Corporation
Inventor: Jeremy Plassmann , Anatoly Yakovlev , Sandeep R. Agrawal , Ali Moharrer , Sanjay Jinturkar , Nipun Agarwal
Abstract: Techniques for computing global feature explanations using adaptive sampling are provided. In one technique, first and second samples from an dataset are identified. A first set of feature importance values (FIVs) is generated based on the first sample and a machine-learned model. A second set of FIVs is generated based on the second sample and the model. If a result of a comparison between the first and second FIV sets does not satisfy criteria, then: (i) an aggregated set is generated based on the last two FIV sets; (ii) a new sample that is double the size of a previous sample is identified from the dataset; (iii) a current FIV set is generated based on the new sample and the model; (iv) determine whether a result of a comparison between the current and aggregated FIV sets satisfies criteria; repeating (i)-(iv) until the result of the last comparison satisfies the criteria.
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公开(公告)号:US20210224221A1
公开(公告)日:2021-07-22
申请号:US17221580
申请日:2021-04-02
Applicant: Oracle International Corporation
Inventor: Navaneeth P. Jamadagni , Ji Eun Jang , Anatoly Yakovlev , Vincent Lee , Guanghua Shu , Mark Semmelmeyer
IPC: G06F13/42
Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.
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公开(公告)号:US11024589B2
公开(公告)日:2021-06-01
申请号:US16159448
申请日:2018-10-12
Applicant: Oracle International Corporation
Inventor: Michael Henry Soltau Dayringer , Anatoly Yakovlev , Ji Eun Jang , Hesam Fathi Moghadam , David Hopkins
Abstract: Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system.
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