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公开(公告)号:US12094841B2
公开(公告)日:2024-09-17
申请号:US17306870
申请日:2021-05-03
Applicant: Oracle International Corporation
Inventor: Michael Henry Soltau Dayringer , Anatoly Yakovlev , Ji Eun Jang , Hesam Fathi Moghadam , David Hopkins
CPC classification number: H01L23/645 , G05F1/462 , H01L23/5227 , H01L24/17 , H02M1/14 , H02M3/158 , H01F27/24 , H01L2924/1206 , H02M1/0048
Abstract: Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system.
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公开(公告)号:US10983944B2
公开(公告)日:2021-04-20
申请号:US16251066
申请日:2019-01-17
Applicant: Oracle International Corporation
Inventor: Navaneeth P. Jamadagni , Ji Eun Jang , Anatoly Yakovlev , Vincent Lee , Guanghua Shu , Mark Semmelmeyer
Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.
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公开(公告)号:US20240404966A1
公开(公告)日:2024-12-05
申请号:US18801005
申请日:2024-08-12
Applicant: Oracle International Corporation
Inventor: Michael Henry Soltau Dayringer , Anatoly Yakovlev , Ji Eun Jang , Hesam Fathi Moghadam , David Hopkins
Abstract: Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system.
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公开(公告)号:US11561923B2
公开(公告)日:2023-01-24
申请号:US17221580
申请日:2021-04-02
Applicant: Oracle International Corporation
Inventor: Navaneeth P. Jamadagni , Ji Eun Jang , Anatoly Yakovlev , Vincent Lee , Guanghua Shu , Mark Semmelmeyer
Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.
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公开(公告)号:US20210257317A1
公开(公告)日:2021-08-19
申请号:US17306870
申请日:2021-05-03
Applicant: Oracle International Corporation
Inventor: Michael Henry Soltau Dayringer , Anatoly Yakovlev , Ji Eun Jang , Hesam Fathi Moghadam , David Hopkins
Abstract: Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system.
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公开(公告)号:US20190115308A1
公开(公告)日:2019-04-18
申请号:US16159448
申请日:2018-10-12
Applicant: Oracle International Corporation
Inventor: Michael Henry Soltau Dayringer , Anatoly Yakovlev , Ji Eun Jang , Hesam Fathi Moghadam , David Hopkins
IPC: H01L23/64 , H01L23/522 , H01L23/00 , G05F1/46
Abstract: Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system.
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公开(公告)号:US20210224221A1
公开(公告)日:2021-07-22
申请号:US17221580
申请日:2021-04-02
Applicant: Oracle International Corporation
Inventor: Navaneeth P. Jamadagni , Ji Eun Jang , Anatoly Yakovlev , Vincent Lee , Guanghua Shu , Mark Semmelmeyer
IPC: G06F13/42
Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.
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公开(公告)号:US11024589B2
公开(公告)日:2021-06-01
申请号:US16159448
申请日:2018-10-12
Applicant: Oracle International Corporation
Inventor: Michael Henry Soltau Dayringer , Anatoly Yakovlev , Ji Eun Jang , Hesam Fathi Moghadam , David Hopkins
Abstract: Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system.
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公开(公告)号:US20200233832A1
公开(公告)日:2020-07-23
申请号:US16251066
申请日:2019-01-17
Applicant: Oracle International Corporation
Inventor: Navaneeth P. Jamadagni , Ji Eun Jang , Anatoly Yakovlev , Vincent Lee , Guanghua Shu , Mark Semmelmeyer
IPC: G06F13/42
Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.
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