公开(公告)号：US10983944B2

公开(公告)日：2021-04-20

申请号：US16251066

申请日：2019-01-17

Applicant: Oracle International Corporation

Inventor： Navaneeth P. Jamadagni ,  Ji Eun Jang ,  Anatoly Yakovlev ,  Vincent Lee ,  Guanghua Shu ,  Mark Semmelmeyer

IPC: G06F13/42 ,  G06F13/40

Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

公开(公告)号：US11561923B2

公开(公告)日：2023-01-24

申请号：US17221580

申请日：2021-04-02

Applicant: Oracle International Corporation

Inventor： Navaneeth P. Jamadagni ,  Ji Eun Jang ,  Anatoly Yakovlev ,  Vincent Lee ,  Guanghua Shu ,  Mark Semmelmeyer

IPC: G06F13/40 ,  G06F13/42

Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

公开(公告)号：US10656205B2

公开(公告)日：2020-05-19

申请号：US15886566

申请日：2018-02-01

Applicant: Oracle International Corporation

Inventor： Mark Semmelmeyer ,  Ali Vahidsafa ,  Sebastian Turullols ,  Scott Cooke ,  Senthilkumar Diraviam ,  Preethi Sama

IPC: G01R31/3183 ,  G01R31/28 ,  G01R31/319 ,  G01R31/317

Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.

公开(公告)号：US20210224221A1

公开(公告)日：2021-07-22

申请号：US17221580

申请日：2021-04-02

Applicant: Oracle International Corporation

Inventor： Navaneeth P. Jamadagni ,  Ji Eun Jang ,  Anatoly Yakovlev ,  Vincent Lee ,  Guanghua Shu ,  Mark Semmelmeyer

IPC: G06F13/42

Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

公开(公告)号：US20200233832A1

公开(公告)日：2020-07-23

申请号：US16251066

申请日：2019-01-17

Applicant: Oracle International Corporation

Inventor： Navaneeth P. Jamadagni ,  Ji Eun Jang ,  Anatoly Yakovlev ,  Vincent Lee ,  Guanghua Shu ,  Mark Semmelmeyer

IPC: G06F13/42

Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.