公开(公告)号：US20030064598A1

公开(公告)日：2003-04-03

申请号：US10195355

申请日：2002-07-15

Applicant: ProMOS Technologies, Inc.

Inventor： Jesse Chung ,  Hsiao-Lei Wang ,  Hung-Kwei Liao

IPC: H01L021/311

CPC classification number: H01L27/10867 ,  H01L21/743

Abstract: A method of forming a buried strap comprising the following sequential steps. A substrate having a pad oxide layer formed thereover is provided. A masking layer is formed over the pad oxide layer. The masking layer, pad oxide layer and substrate are etched to form a trench within the substrate. The trench having an outer sidewall and an upper portion. The upper portion of the trench is lined with a collar. A poly plate is formed within the trench. The poly plate and collar are etched below the substrate to form a recessed poly plate and a recessed collar and exposing a portion of outer sidewall of trench. Ions are implanted into the substrate through exposed outer sidewall of trench by gas phase doping. A SiN sidewall layer is formed over the exposed outer sidewall of trench at a temperature sufficient to diffuse the implanted ions further into the substrate to form the buried strap.

Abstract translation: 一种形成掩埋带的方法，包括以下顺序步骤。 提供了具有形成在其上的衬垫氧化物层的衬底。 在衬垫氧化物层上形成掩模层。 蚀刻掩模层，衬垫氧化物层和衬底以在衬底内形成沟槽。 沟槽具有外侧壁和上部。 沟槽的上部衬有一个领。 在沟槽内形成多晶硅板。 多晶板和套环被蚀刻在基底下方以形成凹入的多晶硅板和凹入的套环，并暴露沟槽外侧壁的一部分。 通过气相掺杂，通过暴露的沟槽的外侧壁将离子注入到衬底中。 在足以将注入的离子进一步扩散到衬底中以形成掩埋带的温度下，在沟槽的暴露的外侧壁上形成SiN侧壁层。

公开(公告)号：US20020016035A1

公开(公告)日：2002-02-07

申请号：US09816356

申请日：2001-03-26

Applicant: ProMOS Technologies, Inc.

Inventor： Chao-Chueh Wu ,  Sheng-Fen Chiu ,  Jesse Chung ,  Hsiao-Lei Wang

IPC: H01L021/8242 ,  H01L021/20

CPC classification number: H01L27/1087

Abstract: A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad Si3N4 uniformity for increasing process yields. The method utilizes a thicker pad Si3N4 as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si3N4 layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si3N4 layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si3N4 layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si3N4 layer to provide a more reliable structure for further processing.

Abstract translation: 实现了一种用于在晶片边缘处制造具有减小的沟槽刻面的DRAM电路的改进的深沟槽电容器的方法，并且改善了焊盘Si3N4均匀性以提高工艺产量。 该方法利用较厚的焊盘Si 3 N 4作为用于蚀刻深沟槽的硬掩模的一部分。 然后，在通过一系列工艺步骤形成深沟槽电容器之后，形成浅沟槽隔离（STI）。 该方法利用在较厚的焊盘Si3N4层中蚀刻浅沟槽并进入硅衬底。 将第二绝缘层沉积并抛光（CMP）到焊盘Si3N4层中。 一个关键特征是使用第二掩模来保护衬底中心，同时部分地蚀刻由固化地由CMP产生的衬底边缘处的衬垫Si3N4层的较厚部分。 这使焊盘Si3N4层的不均匀性最小化，以提供用于进一步处理的更可靠的结构。

公开(公告)号：US20030134468A1

公开(公告)日：2003-07-17

申请号：US10043477

申请日：2002-01-11

Applicant: ProMOS Technologies, Inc.

Inventor： Hsiao-Lei Wang ,  Chao-Hsi (Jesse) Chung ,  Hung-Kwei Liao

IPC: H01L021/8242 ,  H01L027/108

CPC classification number: H01L29/66181 ,  H01L27/1087 ,  H01L29/945

Abstract: A method of increasing DRAM cell capacitance via formation of deep, wide diameter trench capacitor structures, has been developed. An underlying semiconductor substrate is used to accommodate deep, wide diameter trench capacitor structures while an overlying, bonded, thinned semiconductor substrate is used to accommodate narrow diameter trench structures, in turn used for communication to the underlying deep trench capacitor structures, as well as to accommodate the elements of the DRAM device, such as the transfer gate transistors. The use of an underlying semiconductor substrate for accommodation of the trench capacitor structures allows a wider diameter structures to be used, thus reducing patterning difficulties encountered when forming narrow diameter, deep trench capacitor structures.

Abstract translation: 已经开发了通过形成深的，宽直径的沟槽电容器结构来增加DRAM单元电容的方法。 下面的半导体衬底用于容纳深的，宽直径的沟槽电容器结构，而覆盖的，结合的，变薄的半导体衬底被用于适应窄直径的沟槽结构，然后又用于与下面的深沟槽电容器结构的通信，以及 容纳诸如传输门晶体管的DRAM器件的元件。 使用底层半导体衬底来容纳沟槽电容器结构允许使用更宽的直径结构，从而减少当形成窄直径的深沟槽电容器结构时遇到的图案化困难。