公开(公告)号：US20180136967A1

公开(公告)日：2018-05-17

申请号：US15354791

申请日：2016-11-17

Applicant: QUALCOMM Incorporated

Inventor： Samar Asbe ,  Qazi Bashir ,  Vipul Gandhi ,  Chris Henroid ,  Mitchel Allen Humpherys ,  Olav Haugan ,  Daren Hall ,  Adam Openshaw ,  Priyesh Sanghvi ,  Brijen Raval

IPC: G06F9/46 ,  G06F21/53 ,  G06F9/455

CPC classification number: G06F9/45558 ,  G06F21/53 ,  G06F21/79 ,  G06F2009/45587

Abstract: In an aspect, an apparatus that includes a first security domain and at least a second security domain obtains, at a virtual machine of the first security domain, a stream identifier associated with the second security domain. The apparatus generates, at the virtual machine of the first security domain, a command to map the stream identifier associated with the second security domain to a first address translation context. The apparatus maps, at a hypervisor device, the first address translation context to a second address translation context that is associated with the second security domain of the stream identifier. The apparatus processes a stream of memory access transactions that includes the stream identifier based on at least the first address translation context or the second address translation context.

公开(公告)号：US10725932B2

公开(公告)日：2020-07-28

申请号：US16204965

申请日：2018-11-29

Applicant: QUALCOMM INCORPORATED

Inventor： Thomas Zeng ,  Samar Asbe ,  Adam Openshaw

IPC: G06F12/00 ,  G06F12/1027 ,  G06F9/455

Abstract: Systems, methods, and computer programs are disclosed for optimizing headless virtual memory management in a system on chip (SoC) with global translation lookaside buffer shootdown. The SoC comprises an application processor configured to execute a headful virtual machine and one or more SoC processing devices configured to execute a corresponding headless virtual machine. The method comprises issuing a virtual machine mapping command with a headless virtual machine having a first virtual machine identifier. In response to the virtual machine mapping command, a current value stored in a hardware register in the application processor is saved. The first virtual machine identifier associated with the headless virtual machine is loaded into the hardware register. A translation lookaside buffer (TLB) invalidate command is issued while the first virtual machine identifier is loaded in the hardware register. Upon completion of translation lookaside buffer synchronization, the current value is restored to the hardware register.

公开(公告)号：US10514943B2

公开(公告)日：2019-12-24

申请号：US15354791

申请日：2016-11-17

Applicant: QUALCOMM Incorporated

Inventor： Samar Asbe ,  Qazi Bashir ,  Vipul Gandhi ,  Chris Henroid ,  Mitchel Allen Humpherys ,  Olav Haugan ,  Daren Hall ,  Adam Openshaw ,  Priyesh Sanghvi ,  Brijen Raval

IPC: G06F9/455 ,  G06F21/53 ,  G06F21/79

Abstract: In an aspect, an apparatus that includes a first security domain and at least a second security domain obtains, at a virtual machine of the first security domain, a stream identifier associated with the second security domain. The apparatus generates, at the virtual machine of the first security domain, a command to map the stream identifier associated with the second security domain to a first address translation context. The apparatus maps, at a hypervisor device, the first address translation context to a second address translation context that is associated with the second security domain of the stream identifier. The apparatus processes a stream of memory access transactions that includes the stream identifier based on at least the first address translation context or the second address translation context.

公开(公告)号：US20190163645A1

公开(公告)日：2019-05-30

申请号：US16204965

申请日：2018-11-29

Applicant: QUALCOMM INCORPORATED

Inventor： THOMAS ZENG ,  Samar Asbe ,  Adam Openshaw

IPC: G06F12/1027 ,  G06F9/455

Abstract: Systems, methods, and computer programs are disclosed for optimizing headless virtual memory management in a system on chip (SoC) with global translation lookaside buffer shootdown. The SoC comprises an application processor configured to execute a headful virtual machine and one or more SoC processing devices configured to execute a corresponding headless virtual machine. The method comprises issuing a virtual machine mapping command with a headless virtual machine having a first virtual machine identifier. In response to the virtual machine mapping command, a current value stored in a hardware register in the application processor is saved. The first virtual machine identifier associated with the headless virtual machine is loaded into the hardware register. A translation lookaside buffer (TLB) invalidate command is issued while the first virtual machine identifier is loaded in the hardware register. Upon completion of translation lookaside buffer synchronization, the current value is restored to the hardware register.