公开(公告)号：US20190065087A1

公开(公告)日：2019-02-28

申请号：US15684838

申请日：2017-08-23

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  Larry Bassel ,  Thomas Zeng ,  Dexter Chun

IPC: G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for reducing memory power consumption. An exemplary method comprises configuring a power saving memory balloon associated with a volatile memory. Memory allocations are steered to the power saving memory balloon. In response to initiating a memory power saving mode, data is migrated from the power saving memory balloon. A power saving feature is executed on the power saving memory balloon while in the memory power saving mode.

公开(公告)号：US09170957B2

公开(公告)日：2015-10-27

申请号：US14014288

申请日：2013-08-29

Applicant: Qualcomm Incorporated

Inventor： Azzedine Touzni ,  Thomas Zeng

IPC: G06F12/14 ,  G06F12/10 ,  G06F15/167 ,  G06F21/60 ,  G06F21/79

CPC classification number: G06F21/606 ,  G06F12/1009 ,  G06F12/1475 ,  G06F12/1483 ,  G06F15/167 ,  G06F21/76 ,  G06F21/79 ,  G06F2212/1052

Abstract: A first processor and a second processor are configured to communicate secure inter-processor communications (IPCs) with each other. The first processor effects secure IPCs and non-secure IPCs using a first memory management unit (MMU) to route the secure and non-secure IPCs via a memory system. The first MMU accesses a first page table stored in the memory system to route the secure IPCs and accesses a second page table stored in the memory system to route the non-secure IPCs. The second processor effects at least secure IPCs using a second MMU to route the secure IPCs via the memory system. The second MMU accesses the second page table to route the secure IPCs.

Abstract translation: 第一处理器和第二处理器被配置为彼此通信安全的处理器间通信（IPC）。 第一个处理器使用第一个内存管理单元（MMU）通过内存系统对安全和非安全的IPC进行路由，从而影响安全的IPC和非安全的IPC。 第一MMU访问存储在存储器系统中的第一页表以路由安全的IPC并访问存储在存储器系统中的第二页表以路由非安全的IPC。 第二个处理器至少使用第二个MMU来保护安全的IPC，以便通过存储系统路由安全的IPC。 第二个MMU访问第二页表以路由安全的IPC。

公开(公告)号：US08959298B2

公开(公告)日：2015-02-17

申请号：US13726537

申请日：2012-12-24

Applicant: QUALCOMM Incorporated

Inventor： Dexter T. Chun ,  Serag Gadelrab ,  Stephen Molloy ,  Thomas Zeng

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F12/0607 ,  G06F13/1647 ,  G06F13/1694

Abstract: Systems and methods are provided for managing performance of a computing device having dissimilar memory types. An exemplary embodiment comprises a method for interleaving dissimilar memory devices. The method involves determining an interleave bandwidth ratio comprising a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio. Memory address requests are distributed from one or more processing units to the dissimilar memory devices according to the interleave bandwidth ratio.

Abstract translation: 提供了用于管理具有不同存储器类型的计算设备的性能的系统和方法。 示例性实施例包括用于交错不同存储器件的方法。 该方法涉及确定包括两个或多个不同存储器件的带宽比的交织带宽比。 不同的存储器件根据交织带宽比进行交织。 存储器地址请求根据交织带宽比从一个或多个处理单元分配到不同的存储器设备。

公开(公告)号：US10042777B2

公开(公告)日：2018-08-07

申请号：US15084886

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Shaul Yohai Yifrach ,  Thomas Zeng

IPC: G06F12/10 ,  G06F12/1027 ,  G06F3/06 ,  G06F12/1081 ,  G06F13/28 ,  G06F12/0891

Abstract: Hardware-based translation lookaside buffer (TLB) invalidation techniques are disclosed. A host system is configured to exchange data with a peripheral component interconnect express PCIE) endpoint (EP). A memory management unit (MMU), which is a hardware element, is included in the host system to provide address translation according to at least one TLB. In one aspect, the MMU is configured to invalidate the at least one TLB in response to receiving at least one TLB invalidation command from the PCIE EP. In another aspect, the PCIE EP is configured to determine that the at least one TLB needs to be invalidated and provide the TLB invalidation command to invalidate the at least one TLB. By implementing hardware-based TLB invalidation in the host system, it is possible to reduce TLB invalidation delay, thus leading to increased data throughput, reduced power consumption, and improved user experience.

公开(公告)号：US20160283262A1

公开(公告)日：2016-09-29

申请号：US15172529

申请日：2016-06-03

Applicant: QUALCOMM Incorporated

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Philip Mueller, JR. ,  Piyush Patel

IPC: G06F9/455 ,  G06F21/44 ,  G06F12/10

CPC classification number: G06F9/45558 ,  G06F9/45533 ,  G06F9/45545 ,  G06F9/5016 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1491 ,  G06F21/44 ,  G06F21/53 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2212/1052 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/68 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28

Abstract: In the various aspects, virtualization techniques may be used to improve performance and reduce the amount of power consumed by selectively enabling a hypervisor operating on a computing device during sandbox sessions. In the various aspects, a high-level operating system may allocate memory such that its intermediate physical addresses are equal to the physical addresses. When the hypervisor is disabled, the hypervisor may suspend second stage translations from intermediate physical addresses to physical addresses. During a sandbox session, the hypervisor may be enabled and resume performing second stage translations.

Abstract translation: 在各个方面，可以使用虚拟化技术来提高性能并且通过在沙盒会话期间选择性地启用在计算设备上操作的管理程序来减少所消耗的功率量。 在各个方面，高级操作系统可以分配存储器，使得其中间物理地址等于物理地址。 当管理程序被禁用时，管理程序可以将中间物理地址的第二级转换挂起到物理地址。 在沙箱会话期间，管理程序可能被启用，并恢复执行第二阶段转换。

公开(公告)号：US09355050B2

公开(公告)日：2016-05-31

申请号：US14072201

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Thomas Zeng ,  Samar Asbe ,  Azzedine Touzni

IPC: G06F13/26 ,  G06F13/24 ,  G06F9/455 ,  G06F9/48

CPC classification number: G06F13/26 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4812 ,  G06F13/24 ,  G06F2009/45579

Abstract: Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interrupts to the trusted execution environment. The interrupt controller may identify a direct assignment value for the non-secure interrupts indicating whether the non-secure interrupt is owned by a high level operating system (HLOS) Guest or a virtual machine manager (VMM), and whether it is a fast or a normal virtual interrupt. The interrupt controller may direct the HLOS Guest owned interrupt to the HLOS Guest while bypassing the VMM. When the HLOS Guest in unavailable, the interrupt may be directed to the VMM to attempt to pass the interrupt to the HLOS Guest until successful.

Abstract translation: 方面包括用于安全，快速和正常的虚拟中断直接分配的装置和方法，其通过包括可信（安全）和非安全执行环境的多个执行环境的处理器管理安全和非安全的虚拟和物理中断。 中断控制器可以识别中断的安全组值，并将可靠执行环境直接安全中断。 中断控制器可以识别非安全中断的直接分配值，指示非安全中断是由高级操作系统（HLOS）来宾还是虚拟机管理器（VMM）拥有，以及它是快速还是快速 一个正常的虚拟中断。 在绕过VMM时，中断控制器可以将HLOS Guest拥有的中断指向HLOS Guest。 当HLOS访客不可用时，中断可能被定向到VMM，以尝试将中断传递给HLOS访客，直到成功。

公开(公告)号：US10310757B2

公开(公告)日：2019-06-04

申请号：US15684838

申请日：2017-08-23

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Larry Bassel ,  Thomas Zeng ,  Dexter Chun

IPC: G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for reducing memory power consumption. An exemplary method comprises configuring a power saving memory balloon associated with a volatile memory. Memory allocations are steered to the power saving memory balloon. In response to initiating a memory power saving mode, data is migrated from the power saving memory balloon. A power saving feature is executed on the power saving memory balloon while in the memory power saving mode.

公开(公告)号：US20160012241A1

公开(公告)日：2016-01-14

申请号：US14861206

申请日：2015-09-22

Applicant: Qualcomm Incorporated

Inventor： AZZEDINE TOUZNI ,  Thomas Zeng

IPC: G06F21/60 ,  G06F15/167 ,  G06F12/14 ,  G06F21/76

CPC classification number: G06F21/606 ,  G06F12/1009 ,  G06F12/1475 ,  G06F12/1483 ,  G06F15/167 ,  G06F21/76 ,  G06F21/79 ,  G06F2212/1052

Abstract: A first processor and a second processor are configured to communicate secure inter-processor communications (IPCs) with each other. The first processor effects secure IPCs and non-secure IPCs using a first memory management unit (MMU) to route the secure and non-secure IPCs via a memory system. The first MMU accesses a first page table stored in the memory system to route the secure IPCs and accesses a second page table stored in the memory system to route the non-secure IPCs. The second processor effects at least secure IPCs using a second MMU to route the secure IPCs via the memory system. The second MMU accesses the second page table to route the secure IPCs.

公开(公告)号：US09015400B2

公开(公告)日：2015-04-21

申请号：US13785877

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Tzung Ren Tzeng ,  Phil J. Bostley

IPC: G06F12/02 ,  G06F12/10 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45533 ,  G06F9/45545 ,  G06F9/45558 ,  G06F12/10 ,  G06F2212/151 ,  G06F2212/171 ,  G06F2212/507 ,  G06F2212/654 ,  G06F2212/684

Abstract: A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at which a stage 1 (S1) page table is stored, the MMU uses the IPA to predict the corresponding PA, thereby avoiding the need to perform any of the S2 table lookups. This greatly reduces the number of lookups that need to be performed when performing these types of HWTW read transactions, which greatly reduces processing overhead and performance penalties associated with performing these types of transactions.

Abstract translation: 提供一种计算机系统和方法，其在发生翻译后备缓冲器（TLB）未命中的情况下减少执行硬件表行走（HWTW）所需的时间量和计算资源。 如果执行阶段2（S2）HWTW以找到存储第1（S1）页表的PA时发生TLB未命中，则MMU使用IPA来预测对应的PA，从而避免执行任何 S2表查找。 这大大减少了执行这些类型的HWTW读取事务时需要执行的查找次数，这大大降低了与执行这些类型的事务相关联的处理开销和性能损失。

公开(公告)号：US10121001B1

公开(公告)日：2018-11-06

申请号：US15629516

申请日：2017-06-21

Applicant: QUALCOMM INCORPORATED

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Satyaki Mukherjee

IPC: G06F7/04 ,  G06F21/55 ,  G06F9/455 ,  G06F9/48

Abstract: Systems for a method for monolithic workload scheduling in a portable computing device (“PCD”) having a hypervisor are disclosed. An exemplary method comprises instantiating a primary virtual machine at a first exception level, wherein the primary virtual machine comprises a monolithic scheduler configured to allocate workloads within and between one or more guest virtual machines in response to one or more interrupts, instantiating a secure virtual machine at the first exception level and instantiating one or more guest virtual machines at the first exception level as well. When an interrupt is received at a hypervisor associated with a second exception level, the interrupt is forwarded to the monolithic scheduler along with hardware usage state data and guest virtual machine usage state data. The monolithic scheduler may, in turn, generate one or more context switches which may comprise at least one intra-VM context switch and at least one inter-VM context switch.