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公开(公告)号：US10089708B2
公开(公告)日：2018-10-02
申请号：US15141519
申请日：2016-04-28
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Lin Chen , Liang Li , Chunhui Mei
Abstract: A texture unit of a graphics processing unit (GPU) may receive a texture data. The texture unit may receive the texture data from the memory. The texture unit may also multiply, by a multiplier circuit of the texture unit, the texture data by at least one constant, where the constant is not associated with a filtering operation, and where the texture data comprises at least one texel. The texture unit may also output, by the texture unit, a result of multiplying the texture data by the at least one constant.
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公开(公告)号：US20180165786A1
公开(公告)日：2018-06-14
申请号：US15377498
申请日：2016-12-13
Applicant: QUALCOMM Incorporated
Inventor： Alexei Vladimirovich Bourd , Maxim Kazakov , Chunhui Mei , Sumesh Udayakumaran
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005 , G06T2210/52
Abstract: Techniques for allowing for concurrent execution of multiple different tasks and preempted prioritized execution of tasks on a shader processor. In an example operation, a driver executed by a central processing unit (CPU) configures GPU resources based on needs of a first “host” shader to allow the first shader to execute “normally” on the GPU. The GPU may observe two sets of tasks, “guest” tasks. Based on, for example, detecting an availability of resources, the GPU may determine a “guest” task may be run while the “host” task is running. A second “guest” shader executes on a GPU by using resources that were configured for the first “host” shader if there are available resources and, in some examples, additional resources are obtained through software-programmable means.
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3.发明授权公开(公告)号：US09626762B2
公开(公告)日：2017-04-18
申请号：US14686696
申请日：2015-04-14
Applicant: QUALCOMM Incorporated
Inventor： Chunhui Mei , Tao Wang , Young In Yeo , Vineet Goel
CPC classification number: G06T7/70 , G06T1/20 , G06T1/60 , G06T13/80 , G06T15/005 , G06T15/80 , G06T2210/12
Abstract: Techniques are described for stochastic rasterization. A graphics processing unit (GPU) may discard samples of bounding polygons that together indicate movement of one or more primitives before a pixel shader process the samples. The GPU may leverage a stencil buffer and stencil test for discarding of such samples.
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公开(公告)号：US09569811B2
公开(公告)日：2017-02-14
申请号：US14316275
申请日：2014-06-26
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Tao Wang , Chunhui Mei , Gang Zhong , Feng Ge
CPC classification number: G06T1/20 , G06T11/40 , G06T15/005 , G09G5/363 , G09G2340/0407 , G09G2360/122
Abstract: In an example, a method for rendering graphics data includes rendering pixels of a first bin of a plurality of bins, wherein the pixels of the first bin are associated with a first portion of an image, and rendering, to the first bin, one or more pixels that are located outside the first portion of the image and associated with a second, different bin of the plurality of bins. The method also includes rendering the one or more pixels associated with the second bin to the second bin, such that the one or more pixels are rendered to both the first bin and the second bin.
Abstract translation: 在一个示例中，用于渲染图形数据的方法包括渲染多个箱的第一仓的像素，其中第一仓的像素与图像的第一部分相关联，并且向第一仓中呈现一个或 更多的像素位于图像的第一部分之外并且与多个箱的第二不同仓相关联。 该方法还包括将与第二仓相关联的一个或多个像素渲染到第二仓，使得一个或多个像素被渲染到第一仓和第二仓。
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公开(公告)号：US09123168B2
公开(公告)日：2015-09-01
申请号：US13754005
申请日：2013-01-30
Applicant: QUALCOMM Incorporated
Inventor： Chunhui Mei , Nariman Moezzi Madani , Vineet Goel , Usame Ceylan , Guofang Jiao
CPC classification number: G06T17/20 , G06T15/005
Abstract: Systems and methods for a tessellation are described. For tessellation, a tessellation unit may divide a domain into a plurality of portions, where at least one portion is a contiguous portion. The tessellation unit may output domain coordinates of primitives along diagonal strips within the contiguous portion to increase the likelihood that patch coordinates that correspond to the domain coordinates are stored in a reuse buffer.
Abstract translation: 描述了细分的系统和方法。 为了细分，镶嵌单元可以将域划分成多个部分，其中至少一个部分是连续部分。 细分单元可以输出连续部分内沿着对角条纹的基元的域坐标，以增加对应于域坐标的修补坐标被存储在重用缓冲器中的可能性。
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Patent Agency Ranking
公开(公告)号：US20150235341A1
公开(公告)日：2015-08-20
申请号：US14182976
申请日：2014-02-18
Applicant: QUALCOMM Incorporated
Inventor： Chunhui Mei , Vineet Goel , Donghyun Kim
CPC classification number: G06T1/60 , G06T1/20 , G06T15/005 , G06T15/80
Abstract: A graphics processing unit (GPU) may allocate a shared data channel in on-chip graphics memory of the GPU that is shared by at least two stages of a graphics processing pipeline. Shader units in the GPU may execute the at least two stages of the graphics processing pipeline. The GPU may store, in the shared data channel in on-chip graphics memory, data produced by each of the at least two stages of the graphics processing pipeline executing on the shader units.
Abstract translation: 图形处理单元（GPU）可以在图形处理流水线的至少两个阶段共享的GPU的片上图形存储器中分配共享数据信道。 GPU中的着色器单元可以执行图形处理流水线的至少两个阶段。 GPU可以在片上图形存储器的共享数据通道中存储在着色器单元上执行的图形处理流水线的至少两个阶段中的每一个生成的数据。
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公开(公告)号：US20150095914A1
公开(公告)日：2015-04-02
申请号：US14043562
申请日：2013-10-01
Applicant: QUALCOMM Incorporated
Inventor： Chunhui Mei , Alexei Vladimirovich Bourd , Lin Chen
CPC classification number: G06F9/4843 , G06F9/3887 , G06F9/522 , G06T1/20
Abstract: A device includes a memory, and at least one programmable processor configured to determine, for each warp of a plurality of warps, whether a Boolean expression is true for a corresponding thread of each warp, pause execution of each warp having a corresponding thread for which the expression is true, determine a number of active threads for each of the plurality of warps for which the expression is true, sort the plurality of warps for which the expression is true based on the number of active threads in each of the plurality of warps, swap thread data of an active thread of a first warp of the plurality of warps with thread data of an inactive thread of a second warp of the plurality of warps, and resume execution of the at least one of the plurality of warps for which the expression is true.
Abstract translation: 一种设备包括存储器，以及至少一个可编程处理器，其被配置为针对多个经线的每个翘曲确定布线表达式对于每个翘曲的相应线程是否为真，每个经线的暂停执行具有相应的线程， 表达式是真实的，确定表达式为真的多个经线中的每一个的多个活动线程，基于多个经线中的每一个中的活动线程的数量对表达式为真的多个经线进行排序 通过多个经纱中的第二扭曲的无效线程的线程数据交换多个经纱中的第一翘曲的活动线程的线程数据，并且恢复多个经线中的至少一个经线的执行， 表达是真实的。
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公开(公告)号：US10026145B2
公开(公告)日：2018-07-17
申请号：US15377498
申请日：2016-12-13
Applicant: QUALCOMM Incorporated
Inventor： Alexei Vladimirovich Bourd , Maxim Kazakov , Chunhui Mei , Sumesh Udayakumaran
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005 , G06T2210/52
Abstract: Techniques for allowing for concurrent execution of multiple different tasks and preempted prioritized execution of tasks on a shader processor. In an example operation, a driver executed by a central processing unit (CPU) configures GPU resources based on needs of a first “host” shader to allow the first shader to execute “normally” on the GPU. The GPU may observe two sets of tasks, “guest” tasks. Based on, for example, detecting an availability of resources, the GPU may determine a “guest” task may be run while the “host” task is running. A second “guest” shader executes on a GPU by using resources that were configured for the first “host” shader if there are available resources and, in some examples, additional resources are obtained through software-programmable means.
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公开(公告)号：US20170316540A1
公开(公告)日：2017-11-02
申请号：US15141519
申请日：2016-04-28
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Lin Chen , Liang Li , Chunhui Mei
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005 , G06T15/04 , G06T15/80 , G06T2200/28
Abstract: A texture unit of a graphics processing unit (GPU) may receive a texture data. The texture unit may receive the texture data from the memory. The texture unit may also multiply, by a multiplier circuit of the texture unit, the texture data by at least one constant, where the constant is not associated with a filtering operation, and where the texture data comprises at least one texel. The texture unit may also output, by the texture unit, a result of multiplying the texture data by the at least one constant.
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公开(公告)号：US09652284B2
公开(公告)日：2017-05-16
申请号：US14043562
申请日：2013-10-01
Applicant: QUALCOMM Incorporated
Inventor： Chunhui Mei , Alexei Vladimirovich Bourd , Lin Chen
CPC classification number: G06F9/4843 , G06F9/3887 , G06F9/522 , G06T1/20
Abstract: A device includes a memory, and at least one programmable processor configured to determine, for each warp of a plurality of warps, whether a Boolean expression is true for a corresponding thread of each warp, pause execution of each warp having a corresponding thread for which the expression is true, determine a number of active threads for each of the plurality of warps for which the expression is true, sort the plurality of warps for which the expression is true based on the number of active threads in each of the plurality of warps, swap thread data of an active thread of a first warp of the plurality of warps with thread data of an inactive thread of a second warp of the plurality of warps, and resume execution of the at least one of the plurality of warps for which the expression is true.
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