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    Memory request arbitration
    1.
    发明授权
    Memory request arbitration 有权

    公开(公告)号：US10572399B2

    公开(公告)日：2020-02-25

    申请号：US15209346

    申请日：2016-07-13

    Applicant: QUALCOMM Incorporated

    Inventor： Maxim Kazakov

    IPC: G06F3/06 ,  G06F13/16 ,  G06F9/46

    Abstract: In an example, a method of arbitrating memory requests may include tagging a first batch of memory requests with first metadata identifying that the first batch of memory requests originates from a first group of threads. The method may include tagging a second batch of memory requests with second metadata identifying that the second batch of memory requests originates from the first group of threads. The method may include storing the first and second batches of memory requests in a conflict arbitration queue. The method may include performing, using the first metadata and the second metadata, conflict arbitration between only the first batch of memory of requests and the second batch of memory requests stored in the conflict arbitration queue, which may include at least one other batch of memory requests stored that originates from a group of threads different from the first group of threads stored therein.

    RESOURCE SHARING ON SHADER PROCESSOR OF GPU
    2.
    发明申请
    RESOURCE SHARING ON SHADER PROCESSOR OF GPU 审中-公开

    公开(公告)号：US20180165786A1

    公开(公告)日：2018-06-14

    申请号：US15377498

    申请日：2016-12-13

    Applicant: QUALCOMM Incorporated

    Inventor： Alexei Vladimirovich Bourd ,  Maxim Kazakov ,  Chunhui Mei ,  Sumesh Udayakumaran

    IPC: G06T1/20 ,  G06T15/00

    CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

    Abstract: Techniques for allowing for concurrent execution of multiple different tasks and preempted prioritized execution of tasks on a shader processor. In an example operation, a driver executed by a central processing unit (CPU) configures GPU resources based on needs of a first “host” shader to allow the first shader to execute “normally” on the GPU. The GPU may observe two sets of tasks, “guest” tasks. Based on, for example, detecting an availability of resources, the GPU may determine a “guest” task may be run while the “host” task is running. A second “guest” shader executes on a GPU by using resources that were configured for the first “host” shader if there are available resources and, in some examples, additional resources are obtained through software-programmable means.

    MEMORY REQUEST ARBITRATION
    3.
    发明申请
    MEMORY REQUEST ARBITRATION 审中-公开

    公开(公告)号：US20180018097A1

    公开(公告)日：2018-01-18

    申请号：US15209346

    申请日：2016-07-13

    Applicant: QUALCOMM Incorporated

    Inventor： Maxim Kazakov

    IPC: G06F3/06 ,  G06F9/46

    Abstract: In an example, a method of arbitrating memory requests may include tagging a first batch of memory requests with first metadata identifying that the first batch of memory requests originates from a first group of threads. The method may include tagging a second batch of memory requests with second metadata identifying that the second batch of memory requests originates from the first group of threads. The method may include storing the first and second batches of memory requests in a conflict arbitration queue. The method may include performing, using the first metadata and the second metadata, conflict arbitration between only the first batch of memory of requests and the second batch of memory requests stored in the conflict arbitration queue, which may include at least one other batch of memory requests stored that originates from a group of threads different from the first group of threads stored therein.

    REGISTER SPILL MANAGEMENT FOR GENERAL PURPOSE REGISTERS (GPRs)
    4.
    发明申请
    REGISTER SPILL MANAGEMENT FOR GENERAL PURPOSE REGISTERS (GPRs) 有权
    一般用途注册登记管理（GPR）

    公开(公告)号：US20170053374A1

    公开(公告)日：2017-02-23

    申请号：US14828215

    申请日：2015-08-17

    Applicant: QUALCOMM Incorporated

    Inventor： Lee Howes ,  Maxim Kazakov

    IPC: G06T1/20 ,  G06T1/60 ,  G06F3/06

    CPC classification number: G06T1/20 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0683 ,  G06F8/441 ,  G06F9/30127 ,  G06F9/30138 ,  G06F9/462 ,  G06T1/60

    Abstract: Techniques are described for copying data only from a subset of memory locations allocated to a set of instructions to free memory locations for higher priority instructions to execute. Data from a dynamic portion of one or more general purpose registers (GPRs) allocated to the set of instructions may be copied and stored to another memory unit while data from a static portion of the one or more GPRs allocated to the set of instructions may not be copied and stored to another memory unit.

    Abstract translation: 描述了仅将分配给一组指令的存储器位置的子集的数据复制到用于执行更高优先级指令的空闲存储器位置的技术。 分配给该组指令的一个或多个通用寄存器（GPR）的动态部分的数据可以被复制并存储到另一存储器单元，而来自分配给该组指令的一个或多个GPR的静态部分的数据可能不 复制并存储到另一个存储单元。

    Vertex shaders for binning based graphics processing
    8.
    发明授权
    Vertex shaders for binning based graphics processing 有权

    公开(公告)号：US10062139B2

    公开(公告)日：2018-08-28

    申请号：US15218808

    申请日：2016-07-25

    Applicant: QUALCOMM Incorporated

    Inventor： Maxim Kazakov ,  Andrew Evan Gruber

    IPC: G06T1/20 ,  G06T1/60 ,  G06T15/80 ,  G06T15/00

    CPC classification number: G06T1/20 ,  G06T15/005

    Abstract: This disclosure describes examples of using two vertex shaders each one during different graphics processing passes in a binning architecture for graphics processing. A first vertex shader processes subset of attributes of a vertex in a binning pass, where the subset of attributes include those that contribute to visibility determination and attributes that may benefit from being processed with a vertex shader that provides functional flexibility. A second, different vertex shader processes another subset of attributes of the vertex in the rendering pass.

    Resource sharing on shader processor of GPU
    9.
    发明授权
    Resource sharing on shader processor of GPU 有权

    公开(公告)号：US10026145B2

    公开(公告)日：2018-07-17

    申请号：US15377498

    申请日：2016-12-13

    Applicant: QUALCOMM Incorporated

    Inventor： Alexei Vladimirovich Bourd ,  Maxim Kazakov ,  Chunhui Mei ,  Sumesh Udayakumaran

    IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

    CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

    Abstract: Techniques for allowing for concurrent execution of multiple different tasks and preempted prioritized execution of tasks on a shader processor. In an example operation, a driver executed by a central processing unit (CPU) configures GPU resources based on needs of a first “host” shader to allow the first shader to execute “normally” on the GPU. The GPU may observe two sets of tasks, “guest” tasks. Based on, for example, detecting an availability of resources, the GPU may determine a “guest” task may be run while the “host” task is running. A second “guest” shader executes on a GPU by using resources that were configured for the first “host” shader if there are available resources and, in some examples, additional resources are obtained through software-programmable means.

    VERTEX SHADERS FOR BINNING BASED GRAPHICS PROCESSING
    10.
    发明申请
    VERTEX SHADERS FOR BINNING BASED GRAPHICS PROCESSING 审中-公开

    公开(公告)号：US20180025463A1

    公开(公告)日：2018-01-25

    申请号：US15218808

    申请日：2016-07-25

    Applicant: QUALCOMM Incorporated

    Inventor： Maxim Kazakov ,  Andrew Evan Gruber

    IPC: G06T1/20 ,  G06T15/80 ,  G06T1/60 ,  G06T15/00

    CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T15/80

    Abstract: This disclosure describes examples of using two vertex shaders each one during different graphics processing passes in a binning architecture for graphics processing. A first vertex shader processes subset of attributes of a vertex in a binning pass, where the subset of attributes include those that contribute to visibility determination and attributes that may benefit from being processed with a vertex shader that provides functional flexibility. A second, different vertex shader processes another subset of attributes of the vertex in the rendering pass.

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