公开(公告)号：US11636057B2

公开(公告)日：2023-04-25

申请号：US17390215

申请日：2021-07-30

Applicant: QUALCOMM INCORPORATED

Inventor： Engin Ipek ,  Bohuslav Rychlik ,  George Patsilaras ,  Prajakt Kulkarni ,  Can Hankendi ,  Fahad Ali ,  Jeffrey Gemar ,  Matthew Severson

IPC: G06F13/16 ,  H03M5/14

Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.

公开(公告)号：US20240264950A1

公开(公告)日：2024-08-08

申请号：US18163446

申请日：2023-02-02

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Engin Ipek ,  Goran Goran ,  Hamza Omar ,  Bohuslav Rychlik ,  Jeffrey Gemar ,  Matthew Severson ,  Andrew Edmund Turner

IPC: G06F12/126 ,  G06F12/0888

CPC classification number: G06F12/126 ,  G06F12/0888 ,  G06F2212/502

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

公开(公告)号：US12182036B2

公开(公告)日：2024-12-31

申请号：US18163446

申请日：2023-02-02

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Engin Ipek ,  Goran Goran ,  Hamza Omar ,  Bohuslav Rychlik ,  Jeffrey Gemar ,  Matthew Severson ,  Andrew Edmund Turner

IPC: G06F12/126 ,  G06F12/0888

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

公开(公告)号：US20230359373A1

公开(公告)日：2023-11-09

申请号：US17661810

申请日：2022-05-03

Applicant: QUALCOMM Incorporated

Inventor： Engin Ipek ,  Hamza Omar ,  Bohuslav Rychlik ,  Saumya Ranjan Kuanr ,  Behnam Dashtipour ,  Michael Hawjing Lo ,  Jeffrey Gemar ,  Matthew Severson ,  George Patsilaras ,  Andrew Edmund Turner

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0673

Abstract: Selective refresh techniques for memory devices are disclosed. In one aspect, a memory device that is used with an application that has frequent repeated read or write commands to certain memory segments may be able to set a flag or similar indication that exempts these certain memory segments from being actively refreshed. By exempting these memory segments from being actively refreshed, these memory segments are continuously available, thereby improving performance. Likewise, because these memory segments are so frequently the subject of a read or write command, these memory segments are indirectly refreshed through the execution of the read or write command.