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    CONFIGURABLE SPREADING FUNCTION FOR MEMORY INTERLEAVING
    1.
    发明申请
    CONFIGURABLE SPREADING FUNCTION FOR MEMORY INTERLEAVING 有权
    用于存储器交互的可配置扩展功能

    公开(公告)号：US20150095595A1

    公开(公告)日：2015-04-02

    申请号：US14251626

    申请日：2014-04-13

    Applicant: QUALCOMM Incorporated

    Inventor： Feng WANG ,  Bohuslav RYCHLIK ,  Anwar Q. ROHILLAH

    IPC: G06F12/06

    CPC classification number: G06F12/0607 ,  G06F2212/1016

    Abstract: A method of interleaving a memory by mapping address bits of the memory to a number N of memory channels iteratively in successive rounds, wherein in each round except the last round: selecting a unique subset of address bits, determining a maximum number (L) of unique combinations possible based on the selected subset of address bits, mapping combinations to the N memory channels a maximum number of times (F) possible where each of the N memory channels gets mapped to an equal number of combinations, and if and when a number of combinations remain (K, which is less than N) that cannot be mapped, one to each of the N memory channels, entering a next round. In the last round, mapping remaining most significant address bits, not used in the subsets in prior rounds, to each of the N memory channels.

    Abstract translation: 一种通过在连续循环中迭代地将存储器的地址位映射到数量N个存储器通道来交织存储器的方法，其中在除了最后一轮之外的每个循环中：选择唯一的地址位子集，确定最大数目（L） 基于所选择的地址位子集可能的唯一组合，将N个存储器通道中的每一个映射到相等数量的组合的最大次数（F）映射到N个存储器通道，以及如果和何时一个数字 的组合保持（K小于N），N个存储器通道中的每一个输入下一轮。 在最后一轮中，将剩余的最高有效地址位映射到N个存储器通道中的每一个。

    SYSTEM AND METHOD FOR IMPROVED MEMORY PERFORMANCE USING CACHE LEVEL HASHING
    2.
    发明申请
    SYSTEM AND METHOD FOR IMPROVED MEMORY PERFORMANCE USING CACHE LEVEL HASHING 有权

    公开(公告)号：US20170249249A1

    公开(公告)日：2017-08-31

    申请号：US15054295

    申请日：2016-02-26

    Applicant: QUALCOMM INCORPORATED

    Inventor： Feng WANG ,  Bohuslav RYCHLIK

    IPC: G06F12/08

    CPC classification number: G06F12/0811 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0871 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/313

    Abstract: Various embodiments of methods and systems for cache-level memory management in a system on a chip (“SoC”) are disclosed. Memory utilization is optimized in certain embodiments through application of customized hashing algorithms at the lower level cache of individual application clients. Advantageously, for those application clients that do not require or benefit from hashing transaction traffic their transactions are not subjected to hashing. For those application clients that do benefit from hashing transaction traffic in order to minimize page conflicts at a double data rate (“DDR”) memory device, each client further benefits from a customized, and thus optimized, hashing algorithm. Because transaction streams arrive at the memory controller already hashed, or purposefully unhashed, the need for validating clients during a development phase is minimized.

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